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Part V. The Communications Processor Module
21.2.3.7 Programming the SI RAM
Each SI RAM entry determines the routing of the serial bits and the state of strobe outputs
for one time slot. Figure 21-10 shows the format of an SI RAM entry.
Bit
0
1
Field
LOOP SWTR SSEL4 SSEL3 SSEL2 SSEL1
Reset
R/W
Bit
16
17
Field
Reset
R/W
Table 21-2 describes SI RAM entry Þelds.
Bits
Name
0
LOOP
Loop back on this time slot.
0 Normal mode (no loopback).
1 Loopback for this time slot.
1
SWTR Switch transmit and receive. Valid only in Rx route RAM; ignored in the Tx route RAM. Affects
operation of both L1RXDx and L1TXDx. See Figure 21-11 and the accompanying text.
0 Normal operation of L1TXDx and L1RXDx.
1 Data is sent on L1RXDx and received from L1TXDx for the duration of this entry. Note that erratic
results may occur if the Tx and Rx sections of the TDM do not use a common clock source.
2Ð5
SSELn Strobe select 1Ð4. The four strobes, L1ST[1Ð4], can be assigned to the Rx or the Tx RAM and
asserted/negated in sync with the corresponding L1RCLKx or L1TCLKx. Using active-high logic,
each SSELn will be the value of the corresponding strobe during this time slot. Multiple strobes can
be asserted simultaneously. A strobe can be conÞgured to remain asserted for multiple, consecutive
SI RAM entries; however, if a strobe is asserted on the last entry in the table, the strobe is negated
after the last entry Þnishes processing.
Notes: The corresponding parallel I/O pins (either port B or C) must be conÞgured for strobe
operation; see Chapter 34, ÒParallel I/O Ports.Ó
If the same strobe is used in more than one set of entries (in the Rx SI RAM for TDMa and the Tx SI
RAM for TDMb, for example), the assertion of the strobe corresponds to the logical OR of all
possible sources. It is recommended that a given strobe be used in only one set of SI RAM entries.
6
Ñ
Reserved, should be cleared.
7Ð9
CSEL
Channel select. Indicates which channel the time slot is routed to.
000 This time slot is not used. Tx data signal is three-stated; Rx data signal is ignored.
001 SCC1
010 SCC2
011 SCC3
100 SCC4
101 SMC1
110 SMC2
111 This time slot is not used. Also used in SCIT mode to indicate the D channel grant bit.
21-14
2
3
4
5
18
19
20
21
Figure 21-10. SIRAM Entry
Table 21-2. SIRAM Field Descriptions
MPC860 PowerQUICC UserÕs Manual
6
7
8
9
10
Ñ
CSEL
0
R/W
22
23
24
25
26
Ñ
0
R/W
Description
11
12
13
14
15
CNT
BYT
LST
27
28
29
30
31
MOTOROLA
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