Motorola MPC860 PowerQUICC User Manual page 292

Part III. Configuration
Table 11-10 describes SIMASK Þelds.
Bits Name
0 IRQ0 Interrupt request 0. Enables/disables updating SIVEC[INTC]. IRQ0 generates an NMI regardless of
this bit.
1, 3, 5, LVMn Level mask 0Ð7. When set, these bits enable an internal interrupt request to be generated.
7, 9, 11, 0 Disable generation of an interrupt request bit in SIPEND.
13, 15 1 Enable generation of an interrupt request bit in SIPEND.
2, 4, 6, IRMn Interrupt request mask 1Ð7. When set, these bits enable an IRQ interrupt request to be generated.
8, 10, 0 Disable generation of an interrupt request bit in SIPEND.
12, 14 1 Enable generation of an interrupt request bit in SIPEND.
16Ð31 Ñ Reserved, should be cleared.
The following procedure prevents possible interrupt errors when modifying mask registers,
such as SIMASK:
1. Clear MSR[EE]. (Disable external interrupts to the core.)
2. Modify the mask register.
3. Set MSR[EE]. (Enable external interrupts to the core.)
This mask modiÞcation procedure ensures that an already pending interrupt is not masked
before being serviced.
11.5.4.3 SIU Interrupt Edge/Level Register (SIEL)
Bits in SIEL, shown in Figure 11-12, deÞne interrupts as edge- or level-triggered and
enable/disable their use as wake-up signals in low-power mode.
Bit 0 1 2
Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
Reset
R/W
Addr
Bit 16 17 18
Field
Reset
R/W
Addr
Figure 11-12. SIU Interrupt Edge/Level Register (SIEL)
11-18
Table 11-10. SIMASK Field Descriptions
3 4 5 6
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x018
19 20 21 22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x018
MPC860 PowerQUICC UserÕs Manual
Description
7 8 9 10
R/W
23 24 25 26
Ñ
R/W
11 12 13 14
27 28 29 30
MOTOROLA
15
31