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PIP mask (PIPM) register, 33-10
PIP memory map, 2-9
PIP timing parameters register (PTPR), 33-10
PISCR (periodic interrupt status and control)
register, 11-31
PIT, see Periodic interrupt timer
PITC (periodic count) register, 11-32
PITR (periodic interrupt timer register), 11-33
PLL loss of lock, 12-3
PLPRCR (PLL, low-power, and reset control
register), 15-29
PORESET (power-on reset) signal, 3-8, 13-10
PORn (PCMCIA option register), 17-13
Power control
disabling SCC, 22-27
low-power modes, 15-18
overview, 15-1
Power supply signals, 3-15, 13-20
Power-on reset
description, 12-2
reset sequence, 12-4
Power-on reset settings, 15-7
PowerPC architectural specifications,, 1-1
PowerPC architecture
decrementer, 11-23
exceptions, 7-4
execution units, 4-9
features summary, 4-2
instruction list, D-1, D-9, D-17, D-27, D-38
integer unit, 4-10
levels of the architecture, 4-3
load/store unit, 4-10
MMU compliance, 9-2
MPC860 implementation, 4-1, 4-14
overview, 4-1
programming levels, 4-3
timebase, 11-24
PowerPC little-endian (PPC-LE) mode, A-6
Processor control instructions, D-25
Program flow, tracking, 37-1
Program trace
back trace, 37-5
debug mode, 37-5
description, 37-2
indirect branch instructions, 37-5
queue flush information, 37-4
reconstruction, 37-5
sequential instructions, 37-5
signals, 37-3
special cases, 37-4
window trace, 37-6
Programming the SIU, 11-4
Promiscuous mode, see Transparent mode
PSCR
(PCMCIA
interface
register), 17-9
MOTOROLA
INDEX
status
changed
Index
PSMR (protocol-specific mode register), 22-10
AppleTalk mode, 25-4
transparent mode, 29-8
PSMR
(protocol-specific
(asynchronous HDLC), 26-11
PSMR
(protocol-specific
(BISYNC), 27-10
PSMR
(protocol-specific
(Ethernet), 28-19
PSMR (protocol-specific mode register) (HDLC
mode), 24-7
PSMR (protocol-specific register for UART), 23-13
PTR (program trace) signal, 14-4, 14-30
PVR (processor version register), 5-8
Q
QUICC Block Diagram, 1-5
R
RAM word, 16-36
RCCR (RISC controller configuration register), 19-4
RD/WR (read/write) signal, 3-3, 13-5, 14-3, 14-30
Real-time clock, 11-27
Registers
asychronous HDLC mode
SCCS, 26-10
asynchronous HDLC
DSR, 26-7
GSMR, 26-6
asynchronous HDLC mode
PSMR, 26-11
SCCE, 26-9
SCCM, 26-9
BAR, 37-38
BDLE, 27-8
boundary scan register, 38-3
BSYNC, 27-7
cache control, 8-6
clock/power control
PLPRCR, 15-29
SCCR, 15-27
CMPAÐCMPH, 37-37
communications processor
CPCR, 19-6
RCCR, 19-4
RTER, 19-15
TM_CMD, 19-14
COUNTA/COUNTB, 37-43
CPIC, 35-6
CICR, 35-7
CIMR, 35-9
CIPR, 35-8
CISR, 35-9
mode
register)
mode
register)
mode
register)
Index--9
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