Motorola MPC860 PowerQUICC User Manual page 586

Part V. The Communications Processor Module
Bits 0
Field
Reset
R/W
Addr
Figure 20-14. IDMA1 Status Register (IDSR1) (Single-Buffer Mode)
20.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode)
IDMR1 in single-buffer mode behaves the same way as deÞned above; see
Section 20.3.3.3, ÒIDMA Mask Registers (IDMR1 and IDMR2).Ó Figure 20-14 above
shows the mask registerÕs format in single-buffer mode. IDMR1Õs internal address (IMMR
offset) is 0x914.
20.3.9.4 Burst Timing (Single-Buffer Mode)
A typical single-address burst timing when IDMA1 is in single-buffer mode, is illustrated
in Figure 20-15. The peripheral asserts DREQ0 and waits for SDACK1 to initiate a burst
transfer to memory. The peripheral must negate DREQ0 before the last beat of the transfer;
otherwise, IDMA assumes that another DMA request is pendingÑDCMR[STR] will not
be clearedÑand immediately initiates another transfer. If no buffer is available when this
extra transfer begins, erratic operation occurs.
20-20
1 2
Ñ
0000_0000_0000_0000
MPC860 PowerQUICC UserÕs Manual
3 4
R/W
IMMR + 0x910
5 6
DONE Ñ
MOTOROLA
7