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Table 37-13. Debug Instructions/Data Shifted Into Development Port Shift Register
Sta
Mod
Contro
rt
e
l
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
Note: See Table 37-10 for details on trap enable bits.
Transmissions from the debug port on DSDO begin with a zero or ready bit, indicating that
the core is trying to read an instruction or data from the port. The external development tool
must wait until it sees DSDO go low before sending the next transmission. The control bit
distinguishes instructions from data, allowing the development port to detect that an
instruction was entered when the core was expecting data and vice versa. If this occurs, a
sequence error indication is shifted out in the next serial transmission. The trap enable
function allows the development port to transfer data to the trap enable control register. The
debug port command function allows the development tool to either negate breakpoint
requests, reset the processor, activate, or deactivate the fast download procedure. The NOP
function provides a null operation for use when there is data or a response to be shifted out
of the data register. The appropriate next instruction or command will be determined by the
value of the response or data shifted out.
37.3.2.5.2 Serial Data Out of Development Port
The encoding of data shifted out of the development port shift register in debug mode is the
same as for trap enable mode, as shown in Table 37-12. The valid data encoding is used
when data has been transferred from the core to the development port shift register as the
result of an instruction to move the contents of a GPR to the DPDR. The valid data encoding
has the highest priority of all status outputs and is reported even if an interrupt occurs at the
same time. Because a sequencing error cannot occur when data is valid, there is no priority
conßict with the sequencing error status. Also, an interrupt recognized when there is valid
data is not related to the execution of an instruction, therefore, a valid data status is output
and the interrupt status is saved for the next transmission.
MOTOROLA
Instruction/Data (32 Bits)
Bits 0Ð6
Bits 7Ð31
Core instruction
Core data
Trap enable bits
Not exist
0b001_1111
Not exist
0
Not exist
Chapter 37. System Development and Debugging
Part VI. Debug and Test
Function
Transfer instruction to core
Transfer data to core
Transfer data to trap enable control register
Negate breakpoint requests to core
NOP
37-33
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