Motorola MPC860 PowerQUICC User Manual page 476

Part IV. Hardware Interface
driven in this state until the LAST bit is set in a RAM word. The TODT bit is relevant only
in words read by the UPM after AS is negated.
For a comprehensive discussion of external bus interfacing, see Section 16.8, ÒExternal
Master Support.Ó
CLKOUT
GCLK1_50
GCLK2_50
CSx C1 C2 C3
GPL1 A
TA
WAEN AA
AS
RAM
Word N
Figure 16-46. Wait Mechanism Timing for an External Asynchronous Master
16.7 Handling Devices with Slow or Variable Access
Times
The memory controller provides two ways to interface with slave devices that are very slow
(access time is greater than the maximum allowed by the user programming model) or
cannot guarantee a predeÞned access time (for example some FIFO, hierarchical bus
interface, or dual-port memory devices). These mechanisms are as follows:
¥ The wait mechanismÑUsed only in accesses controlled by the UPM.
MAMR[GPLA4DIS] and MBMR[GPLB4DIS] enable this mechanism.
¥ The external TA mechanism is used only in accesses controlled by the GPCM.
ORx[SETA] speciÞes whether TA is generated internally or externally.
The following examples show how the two mechanisms work.
16-50
C4 C5 C6 C7 C8 C9
B C D
BB CC
RAM
Word N + 1 Word N + 2
MPC860 PowerQUICC UserÕs Manual
C10 C11 C12
E F
RAM
WAIT
DD
RAM
WAIT
Word N
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