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Part III. Configuration
Bit
0
1
Field
Reset
R/W
Addr
Bit
16
17
18
Field
Reset
R/W
Addr
Figure 11-27. Real-Time Clock Alarm Seconds Register (RTSEC)
Table 11-23 describes RTSEC Þelds.
Bits
Name
0Ð13
COUNTER Counter bits (fraction of a second). Bit 13 is always the LSB of the count. It either resets at 8192
or at 9600, as programmed.
14Ð31 Ñ
Reserved. should be cleared.
11.11 The Periodic Interrupt Timer (PIT)
The PIT consists of a 16-bit counter clocked by a PITRTCLK clock supplied by the clock
module. The PIT is not affected by HRESET and RESET; however, it is disabled and reset
by PORESET. It decrements to zero when loaded with a value from the PIT count register
(PITC) and after the timer reaches zero, PS is set and an interrupt is generated if PIE is a 1.
At the next input clock edge, the PITC value is loaded into the counter and the process
repeats. When a new value is loaded into PITC, the PIT is updated, the divider is reset, and
the counter starts counting. If the PS bit is set, an interrupt is generated at the interrupt
controller that remains pending until PS is cleared. If PS is set again, before being cleared,
the interrupt remains pending until PS is cleared. Any write to PITC stops the current
countdown and the count resumes with a new value in the PITC. If the PTE bit is not set,
the PIT is unable to count and retains the old count value. Reading the PIT does not affect it.
11-30
2
3
4
5
6
COUNTER
(IMMR & 0xFFFF0000) + 0x228
19
20
21
22
(IMMR & 0xFFFF0000) + 0x23A
Table 11-23. RTSEC Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7
8
9
10
11
Ñ
R/W
23
24
25
26
27
Ñ
Ñ
R/W
Description
12
13
14
15
Ñ
28
29
30
31
MOTOROLA
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