Motorola MPC860 PowerQUICC User Manual page 911

Part V. The Communications Processor Module
In a polled interrupt scheme, the user must periodically read the CIPR. After a pending
interrupt is handled, clear the corresponding CIPR bit. However, if an event register exists,
clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. Write
ones to clear CIPR bits; writing zeros has no effect.
In a polled interrupt scheme, the user must periodically read the CIPR. After handling a
pending interrupt, clear the corresponding CIPR bit directly for interrupt sources from port
C pins. For all other interrupt sources, however, clear the unmasked event register bits
instead, thus causing the CIPR bit to be cleared. Write ones to clear CIPR bits; writing zeros
has no effect.
The SCCs CIPR bit positions are not changed according to their relative priority (as
determined by CICR[SCxP] and CICR[SPS]). If the error vector is issued in the CIVR, this
means that no CIPR bits were cleared when CIVR[IACK] was set.
35.5.3 CPM Interrupt Mask Register
Each bit in the read/write CPM interrupt mask register (CIMR) corresponds to a CPM
interrupt source indicated in CIPR. The CIPR and CIMR are shown in Figure 35-4. An
interrupt is masked by clearing and enabled by setting the corresponding CIMR bit. Even
if an interrupt is masked, the corresponding CIPR bit is set when an interrupt condition
occurs, but the interrupt request is not passed to the core.
If a CPM interrupt source is requesting interrupt service when its CIMR bit is cleared, the
request stops. If the bit is set later, the core processes previously pending interrupt requests
according to priority.
The CIMR[SCCx] bit positions are unaffected by the relative priority programmed in the
conÞguration register, CICR.
35.5.4 CPM Interrupt In-Service Register (CISR)
Each bit in the CPM interrupt in-service register (CISR) corresponds to a CPM interrupt
source. The CISR, CIPR, and CIMR are shown in Figure 35-4. In a vectored interrupt
environment, the CPIC sets a CISR bit when the core acknowledges the interrupt by setting
CIVR[IACK]. An interrupt service routine must clear IACK after servicing is complete. If
an event register exists for this peripheral, its bits would normally be cleared. Write ones to
clear CISR bits; writing zeros has no effect.
Bits set in this register indicate which interrupt requests are in progress for each CPM
interrupt source. More than one CISR bit can be set if higher priority CPM interrupts are
allowed to interrupt lower priority level interrupts within the same CPM interrupt level. For
example, the TIMER1 interrupt routine could interrupt the TIMER2 interrupt handler. See
Section 35.2.3, ÒNested Interrupts.Ó During this time, the user can set CISR[TIMER1] and
CISR[TIMER2] simultaneously.
The SCCs CISR bit positions are not affected by the relative priority between one another.
MOTOROLA Chapter 35. CPM Interrupt Controller 35-9