Motorola MPC860 PowerQUICC User Manual page 588

Part V. The Communications Processor Module
20.3.11 Interrupts During an IDMA Bus Transfer
The MPC860 supports a synchronous bus structure with provisions allowing a bus master
to detect and respond to errors during a bus cycle. An IDMA channel recognizes the same
bus interrupt sources that the core recognizesÑreset and transfer error acknowledge
(TEA).
¥ ResetÑOn an external reset, an IDMA immediately aborts channel operation,
returns to the idle state, and clears the IDSR. If a bus cycle is in progress, the cycle
is terminated, the control and address/data pins are three-stated, and the bus
ownership is released. Program control passes to the handler at the system reset
interrupt vector (0x00100).
¥ Transfer error acknowledge (TEA)ÑWhen a fatal error occurs during an IDMA bus
cycle, TEA is used to abort the cycle and systematically terminate the channelÕs
operation. The IDMA terminates the current bus cycle, ßags an error in SDSR and
interrupts the core if not masked by SDMR. The IDMA waits for the CPM to reset
before starting any new bus cycles. Note that data read from the source into internal
storage is lost. Program control passes to the handler at the machine check interrupt
vector (0x00200).
The machine check and system reset interrupts are described in Chapter 7, ÒExceptions.Ó
Note that the source or destination device under IDMA handshake control for
single-address transfers may need to monitor TEA to detect a bus exception for the current
bus cycle. TEA terminates the cycle immediately and negates SDACK, which is used to
control the transfer to or from the device.
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