Motorola MPC860 PowerQUICC User Manual page 442

Part IV. Hardware Interface
Table 16-7 describes MCR Þelds.
Bits Name
0Ð1 OP Command opcode. DeÞnes the operation to be executed by the UPM speciÞed in the UM Þeld.
00 WRITE writes the contents of the MDR into the RAM location indexed by MCR[MAD].
01 READ reads the contents of the RAM location indexed by MCR[MAD] and stores it in the MDR.
10 RUN executes the pattern in the RAM array beginning with the RAM word indexed by MCR[MAD]
on the memory bank speciÞed in MCR[MB]. The AMX bits of the UPM RAM word in this
software-initiated pattern must all be set to 0b11. Thus, the address for this pattern is the value
written to MAR. The data bus is not driven.
11 Reserved.
2Ð7 Ñ Reserved, should be cleared.
8 UM User machine. Selects the UPM for this command.
0 UPMA
1 UPMB
9Ð15 Ñ Reserved, should be cleared.
16Ð18 MB Memory bank. Indicates the appropriate CSx pin when a RUN command is executed (000
corresponds to CS0, 001 corresponds to CS1, É, 111 corresponds to CS7)
19 Ñ Reserved, should be cleared.
20Ð23 MCLF Memory command loop Þeld. SpeciÞes how many times a loop is executed for a
(0001 = the loop executes once, 0010 = the loop executes twice, É, 1111 = the loop executes 15
times. Note that 0000 = the loop executes 16 times.)
24Ð25 Ñ Reserved, should be cleared.
26Ð31 MAD Memory array index. SpeciÞes an index to one of 64 RAM words in the RAM array.
16.4.6 Memory Data Register (MDR)
The memory data register (MDR) contains data written to or read from the RAM array for
UPM or
READ WRITE
the MCR.
Bit 0 1
Field
Reset
R/W
Address
Bit 16 17 18
Field
Reset
R/W
Address
16-16
Table 16-7. MCR Field Descriptions
commands. MDR must be set up before issuing a write command to
2 3 4 5 6
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x17C
19 20 21 22
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x17E
Figure 16-12. Memory Data Register (MDR)
MPC860 PowerQUICC UserÕs Manual
Description
7 8 9 10 11
MD
R/W
23 24 25 26 27
MD
R/W
command.
RUN
12 13 14 15
28 29 30 31
MOTOROLA