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After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if
RxBD[I] is set. It moves to the next RxBD in the table and begins moving data to its buffer.
If the next buffer is not available, SCCE[BSY] signiÞes a busy signal that can generate a
maskable interrupt. The receiver reverts to hunt mode when an
command or an error is received. If GSMR_H[REVD] is set, the bit order of each byte is
reversed before it is written to memory.
Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller,
which may cause receiver overruns at higher transmission speeds. The receiver always
checks the CRC of the received frame, according to GSMR_H[TCRC]. If a CRC is not
required, resulting errors can be ignored.
29.4 Achieving Synchronization in Transparent Mode
Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and
the transmit FIFO is preloaded by the SDMA channel, another process must occur before
data can be sent. It is called transmit synchronization. Similarly, once the SCC receiver is
enabled for transparent operation in the GSMR and the RxBD is made empty for the SCC,
receive synchronization must occur before data can be received. An in-line synchronization
pattern or an external synchronization signal can provide bit-level control of the
synchronization process when sending or receiving.
29.4.1 Synchronization in NMSI Mode
The following sections describe synchronization in NMSI mode.
29.4.1.1 In-Line Synchronization Pattern
The transparent channel can be programmed to receive a synchronization pattern. This
pattern is deÞned in the data synchronization register, DSR; see Section 22.1.3, ÒData
Synchronization Register (DSR).Ó Pattern length is speciÞed in GSMR_H[SYNL], as
shown in Table 29-1. See also Section 22.1.1, ÒGeneral SCC Mode Register (GSMR)
Table 29-1. Receiver SYNC Pattern Lengths of the DSR
GSMR_H[SYNL]
Setting
00
01
10
11
If a 4-bit SYNC is selected, reception begins as soon as these four bits are received,
beginning with the Þrst bit following the 4-bit SYNC. The transmitter synchronizes on the
receiver pattern if GSMR_H[RSYN] = 1.
MOTOROLA
0
1
2
3
4
5
An external SYNC signal is used instead of the SYNC pattern in the DSR.
4-bit
8-bit
Chapter 29. SCC Transparent Mode
Part V. The Communications Processor Module
Bit Assignments
6
7
8
9
10
11
16-bit
ENTER HUNT MODE
.Ó
12
13
14
15
29-3
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