Motorola MPC860 PowerQUICC User Manual page 403

15.2.2.4 Disabling the SPLL
For special purposes (e.g. testing), it is possible to disable the SPLL. The SPLL is disabled
if VDDSYN is grounded. In this case, VCOOUT will be equal to OSCCLK/2.
Note that because the skew elimination provided by the SPLL is also disabled, this mode
of operation invalidates the timing of the MPC860. Thus, this mode must not be used as a
normal operating mode; its only valid use is for low-frequency testing of board integrity
during production.
15.3 Clock Signals
The MPC860 uses the following clocks, summarized in Table 15-3. These clocks are
described in the following three sections, grouped by their different sources.
.
Table 15-3.Functionality Summary of the Clocks
Clock
GCLK1C/GCLK2C Basic clocks supplied to the core, the data and instruction caches, and MMUs.
GCLK1/GCLK2 Basic clocks supplied to the SIU, clock module, RISC controller, and most other features in the
CPM
GCLK1_50/GCLK2_5 Optionally divided versions of GCLK1/GCLK2, which are used to clock the GPCM and UPM in
0 the memory controller and to provide the CLKOUT output for the external bus.
BRGCLK Clocks the four baud rate generators and the memory controller refresh timer. This allows the
serial ports to operate at a Þxed frequency and the memory refresh to continue at a uniform
rate even when the rest of the MPC860 is operating at a reduced frequency (e.g. normal low,
doze low)
SYNCCLK Used by the serial synchronization circuitry in the serial ports of the CPM, and includes the SI,
SCCs and SMCs. SYNCCLK performs the function of synchronizing externally generated
clocks before they are used internally. SYNCCLK allows the SI, SCCs, and SMCs to continue
operating at a Þxed frequency, even when the rest of the MPC860 is operating at a reduced
frequency.
CLKOUT Clock Out is an external clock signal used to drive other devices, and thus provide the ability to
operate synchronously with those devices. Equivalent to the internal GCLK2_50 signal.
TMBCLK Clocks the Time Base and Decrementer
PITRTCLK Clocks the Periodic Interrupt Timer and the Real Time Clock
15.3.1 Clocks Derived from the SPLL Output
The MPC860 uses the following 9 internal clock signals, which are derived from the SPLL
output clock (VCOOUT):
¥ General system clocksÑGCLK1C, GCLK2C, GCLK1, GCLK2
¥ Memory controller and external bus clocksÑGCLK1_50, GCLK2_50
¥ Baud rate generator clockÑBRGCLK
¥ Synchronization clocksÑSYNCCLK, SYNCCLKS
MOTOROLA Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
Description
15-9