Motorola MPC860 PowerQUICC User Manual page 516

Part IV. Hardware Interface
17.4.4 PCMCIA Interface General Control Register (PGCRx)
PGCRA or PGCRB, shown in Figure 17-6, are used to reset the PCMCIA cards, disable the
output of the external latches, and specify the source used for a DMA request.
Bit 0 1 2
Field
Reset
R/W
Addr
Bit 16 17 18
Field CxDREQ
Reset
R/W
Addr
Figure 17-6. PCMCIA Interface General Control Register B (PGCRx)
Table 17-11 describes PGCRx Þelds.
Bits Name
0Ð7 CxIREQLVL Card x IREQ interrupt level. Only one bit of this Þeld should be set at any time.
8Ð15 CxSCHLVL Card x STSCHG interrupt level. Only one CASCHLVLx bit should be set at any time.
16Ð17 CxDREQ Card x DREQ. DeÞnes internal DMA request for the on-chip DMA controller (CADREQ
controls channel 0. CBDREQ controls channel 1).
0x Disable internal DMA request from slot x.
10 Enable IOIS16_x as internal DMA request for slot x.
11 Enable SPKR_x as internal DMA request for slot x.
18Ð23 Ñ Reserved, should be cleared.
24 CxOE Card x output enable. CAOE is reßected on OP1 and CBOE is reßected on OP2 used to
three-state the external buffers when the cardÕs power is activated.
25 CxRESET Card x reset. CARESET is reßected on OP0 used to reset card A. CBRESET is reßected on
OP3 used to reset card B.
26Ð31 Ñ Reserved, should be cleared.
17.4.5 PCMCIA Base Registers 0Ð7 (PBR0ÐPBR7)
Setting a bit in the PBR, shown in Figure 17-5, enables the corresponding interrupt.
17-12
3 4 5 6
CxIREQLVL
(IMMR & 0xFFFF0000) + 0x0E4
19 20 21 22
Ñ
(IMMR & 0xFFFF0000) + 0x0E6
Table 17-11. PGCRx Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7 8 9
R/W
23 24 25
CxOE CxRESET
R/W
Description
10 11 12 13 14
CxSCHLVL
26 27 28 29 30
Ñ
MOTOROLA
15
31