Motorola MPC860 PowerQUICC User Manual page 131

¥ Pipelined operation. The LSU pipelines load accesses. Individual cache accesses of
all multiple-register instructions and unaligned accesses are pipelined into the data
cache interface.
¥ Load/store multiple and string instructions synchronize
¥ Load/store breakpoint/watchpoint detection support
¥ The LSU implements cache and TLB management instructions as special bus write
cycles, which are issued to the data cache interface.
Figure 4-5 is a block diagram of the LSU and its two queues. The address queue is a 2-entry
queue shared by all load/store instructions and the integer data queue is a 2-entry, 32-bit
queue that holds integer data.
The LSU has a dedicated writeback bus so that loaded data received from the internal bus
is written directly back to the GPRs.
Address
Queue
and
Increment
To execute multiple/string instructions and unaligned accesses, the LSU increments the EA
to access all necessary data. This allows the LSU to execute unaligned accesses without
stalling the master instruction pipeline.
MOTOROLA
Integer
Unit
Address
Load Data
32-Bit 32-Bit
D-Cache/D-MMU
32-Bit
Interface
Figure 4-5. LSU Functional Block Diagram
Chapter 4. The PowerPC Core
Part II. PowerPC Microprocessor Module
GPRs
Integer Integer
Store Data
32-Bit
LOAD/STORE
UNIT
Integer
32-Bit
Data Queue
32-Bit
CORE
4-11