Motorola MPC860 PowerQUICC User Manual page 912

Part V. The Communications Processor Module
If the error vector is taken, no CISR bit is set. All undeÞned CISR bits return zeros when
read. The extent to which CPM interrupts can interrupt one another is controlled by
selectively clearing the CISR. A new interrupt is processed if it has a higher priority than
the highest priority interrupt having its CISR bit set. Thus, if an interrupt routine sets the
external interrupt enable bit in the core (MSR[EE]) and clears its CISR bit at the beginning
of the interrupt routine, a lower priority interrupt can interrupt a higher one if the lower
priority interrupt has higher priority than any other CISR bits that are currently set.
Therefore, the interrupt service routine should clear its CISR bit at the end.
35.5.5 CPM Interrupt Vector Register (CIVR)
The CPM interrupt vector register (CIVR) is used to identify an interrupt source. The core
uses the IACK bit to acknowledge an interrupt. CIVR can be read at any time.
Bit 0 1 2
Field VN
Reset
R/w
Address
Figure 35-5. CPM Interrupt Vector Register (CIVR)
Table 35-4 describes CIVR Þelds. Section 35.6, ÒInterrupt Handler ExampleÑ
Single-Event Interrupt Source,Ó and Section 35.7, ÒInterrupt Handler ExampleÑ
Multiple-Event Interrupt Source,Ó show how CIVR Þelds are used.
Bits Name
0Ð4 VN Vector number. IdentiÞes the interrupt source. These values are listed in Table 35-2.
5Ð14 Ñ Reserved. Writing to bits 5-15 has no effect because they are always read as zeros.
15 IACK Interrupt acknowledge. When the core sets IACK, CIVR[VN] is updated with a 5-bit vector
corresponding to the sub-block with the highest current priority. IACK is cleared after one clock cycle.
35.6 Interrupt Handler ExampleÑSingle-Event
Interrupt Source
In this example, the CPIC hardware clears CIPR[PC6] during the interrupt acknowledge
cycle. The following steps show how to handle an interrupt source without multiple events.
1. Set CIVR[IACK].
2. Read CIVR[VN] to determine the vector number for the interrupt handler.
3. Handle the interrupt event indicated through the port C6 signal.
4. Clear CISR[PC6].
5. Execute the rfi instruction.
35-10
3 4 5 6
0000_00000_0000_0000
Table 35-4. CIVR Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7 8 9 10 11
0
R/W
0x930
Description
12 13 14 15
IACK
MOTOROLA