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Name
Type
PD[8]
Bidirectional General-Purpose I/O Port D Bit 8ÑBit 8 of the general-purpose I/O port D.
TXD4
PD[7]
Bidirectional General-Purpose I/O Port D Bit 7ÑBit 7 of the general-purpose I/O port D.
RTS3
PD[6]
Bidirectional General-Purpose I/O Port D Bit 6ÑBit 6 of the general-purpose I/O port D.
RTS4
PD[5]
Bidirectional General-Purpose I/O Port D Bit 5ÑBit 5 of the general-purpose I/O port D.
REJECT2
PD[4]
Bidirectional General-Purpose I/O Port D Bit 4ÑBit 4 of the general-purpose I/O port D.
REJECT3
PD[3]
Bidirectional General-purpose I/O Port D Bit 3ÑBit 3 of the general-purpose I/O port D.
REJECT4
TCK
Input
DSCK
TMS
Input
TDI
Input
DSDI
TDO
Output
DSDO
TRST
Input
SPARE[1Ð4]
No-connect
Power Supply
Power
NOTE: * See Figure 13-2.
MOTOROLA
Table 3-1. Signal Descriptions (Continued)
TXD4ÑTransmit data for serial channel 4.
RTS3ÑActive low request to send output indicates that SCC3 is ready to transmit
data.
RTS4ÑActive low request to send output indicates that SCC4 is ready to transmit
data.
REJECT2ÑThis input to SCC2 allows a CAM to reject the current Ethernet frame
after it determines the frame address did not match.
REJECT3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame
after it determines the frame address did not match.
REJECT4ÑThis input to SCC4 allows a CAM to reject the current Ethernet frame
after it determines the frame address did not match.
Provides clock to scan chain logic or for the development port logic.
Controls the scan chain test mode operations.
Input serial data for either the scan chain logic or the development port and
determines the operating mode of the development port at reset.
Output serial data for either the scan chain logic or for the development port.
Reset for the scan chain logic.
Spare signalsÑNot used on current chip revisions. Leave unconnected.
VDDLÑPower supply of the internal logic.
VDDHÑPower supply of the I/O buffers and certain parts of the clock control.
VDDSYNÑPower supply of the PLL circuitry.
KAPWRÑPower supply of the internal OSCM, RTC, PIT, DEC, and TB.
VSSÑGround for circuits, except for the PLL circuitry.
VSSSYN, VSSSYN1ÑGround for the PLL circuitry.
Chapter 3. Hardware Interface Overview
Description
Part I. Overview
3-15
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