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Part II. PowerPC Microprocessor Module
4.5.1 Branch Processing Unit
The branch processing unit differs from the other execution units in that it examines branch
instructions while they are in the IQ. Other instructions are dispatched to the IU and LSU
from IQ0. For details about the performance of various instructions, see Table 4-1.
The core supports the UISA-deÞned static branch prediction. That is, the y bit is used to
provide a hint as to whether the branch the branch is likely to be taken or not taken. No
prediction is done for branches to the link register or count register if the target address is
not ready (see Table 4-1 for details).
4.5.2 Integer Unit
The core implements the following types of integer instructions:
¥ Arithmetic instructions
¥ Compare instructions
¥ Trap instructions
¥ Logical instructions
¥ Rotate and shift instructions
Most integer instructions can execute in one clock cycle. For details about the performance
of the various instructions, see Table 4-1 of this manual.
Note the following special cases:
¥ If an mtspr or mfspr instruction speciÞes an invalid SPR in which spr[0] = 1, a
program exception occurs if the processor is in user mode. Valid SPRs are listed in
Chapter 5, ÒPowerPC Core Register Set.Ó
¥ If divw[o][.] is used to perform either (0x80000000
contents of rD are 0x8000_0000 and if Rc = 1, the contents of the bits in the CR Þeld
0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value.
¥ In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit
implementations. For the MPC860, if L = 1 the instruction form is invalid. The core
ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form
instruction with L = 0.
4.5.3 Load/Store Unit
The load/store unit (LSU) transfers all data between the GPRs and the processorÕs internal
bus. It is implemented as an independent execution unit so that stalls in the memory
pipeline affect the master instruction pipeline only if there is a data dependency.
The following lists the LSUÕs main features:
¥ All instructions implemented in hardware, including unaligned, string, and multiple
accesses
¥ Two-entry load/store instruction address queue
4-10
MPC860 PowerQUICC UserÕs Manual
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