Motorola MPC860 PowerQUICC User Manual page 265

10.1.3 Private Writeback Bus Load
In Figure 10-4, lwz and xor write back in the same clock since they use the writeback bus
in two different ticks (a tick = 1/4 of a processor clock).
lwz r12,64 (SP)
sub r5,r5,3
cror 4,14,1
and r3,r4.r5
xor r4,r3,r5
ori r6,r12.r3
GCLK1
lwz
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
Figure 10-4. Private Writeback Bus Load Timing
10.1.4 Fastest External Load (Data Cache Miss)
Figure 10-5 shows a sub instruction dependent on the value read by the load. It causes three
bubbles in the execution stream. Assuming SCCR[EBDF] = 00, the external clock
(CLKOUT) is shifted 90° from the internal clock (GCLK1).
lwz
r12,64 (SP)
sub
r3,r12,3
addic
r4,r14,1
GCLK1
Fetch lwz
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
MOTOROLA
sub cror
load sub
load sub
lwz
lwz
sub addic
lwz sub
lwz Bubble
lwz
lwz
Figure 10-5. External Load Timing
Chapter 10. Instruction Execution Timing
Part II. PowerPC Microprocessor Module
and xor
cror
and xor
cror and
cror
sub
lwz
Bubble Bubble
lwz
ori
ori
xor ori
and xor ori
lwz
lwz
lwz
Bubble sub
sub
lwz
lwz
lwz
10-3