Motorola MPC860 PowerQUICC User Manual page 1008

Appendixes
Byte-Ordering Mode
BE
TLE
PPC-LE
Note: The MPC860 powers up in BE mode.
A.3 BE Mode
As shown in Table A-1, the MPC860 powers up in BE mode. In BE mode, the caches,
internal registers, the U-bus, and the external bus, all use big-endian byte ordering. In BE
mode, no address modiÞcation nor data-byte-lane swapping is performed by any of the
byte-ordering mechanisms of the MPC860.
The PowerPC architecture deÞnes two bits in the MSR for specifying byte orderingÑLE
(little-endian mode) and ILE (exception little-endian mode). For the MPC860, these bits
only control the addresses generated by the PowerPC core. The LE bit speciÞes the endian
mode for normal core operation and ILE speciÞes the mode to be used when an exception
handler is invoked. That is, when an exception occurs, the ILE bit (as set for the interrupted
process) is copied into MSR[LE] to select the endian mode for the context established by
the exception. For both bits, a value of 0 speciÞes BE mode (or TLE mode, depending on
DC_CST[LES]), and a value of 1 speciÞes PPC-LE mode.
A.4 TLE Mode
When the MPC860 operates in TLE mode, the external bus uses little-endian byte ordering,
so any external agents should use little-endian byte ordering to access memory. Note
however, that internal to the MPC860, the caches and internal registers use big-endian byte
ordering. The byte-ordering mechanisms for TLE mode are shown in Figure A-1.
A-2
Table A-1. Byte-Ordering Parameters
MSR[LE] or
MSR[ILE]
0
0
1
MPC860 PowerQUICC UserÕs Manual
Parameter
DC_CST[LES] FCR[BO]
0 1x
1 1x
0 01
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