Motorola MPC860 PowerQUICC User Manual page 176

Part II. PowerPC Microprocessor Module
7.1 Exceptions
The OEA deÞnes a set of exceptions for PowerPC processors, some of which are optional.
The following sections describe exceptions implemented on the MPC860. Those deÞned
by the OEA are described in Section 7.1.2, ÒPowerPC-DeÞned Exceptions.Ó Section 7.1.3,
ÒImplementation-SpeciÞc Exceptions,Ó describes implementation-speciÞc exceptions.
All exceptions associated with memory are implemented as precise, which means that a
load/store instruction is not complete until all possible error indications are sampled from
the load/store bus. This also implies that a store or nonspeculative load instruction is not
issued to the load/store bus until all previous instructions have completed. If a late error
occurs, a store cycle (or a nonspeculative load cycle) can be issued and aborted.
In each exception handler, when registers SRR0 and SRR1 are saved, MSR[RI] can be set.
Table 7-1 deÞnes the offset value by exception type and the sections that follow describe
each exception in detail. Note that the base is determined by the setting of MSR[IP].
Table 7-1. Offset of First Instruction by Exception Type
Offset Exception
0x00000 Reserved
0x00100 System reset interrupt
0x00200 Machine check interrupt
0x00300 DSI
0x00400 ISI
0x00500 External Interrupt
0x00600 Alignment
0x00700 Program
7-2
OEA-DeÞned Exceptions
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See Section 7.1.2.1, ÒSystem Reset Interrupt (0x00100).Ó
See Section 7.1.2.2, ÒMachine Check Interrupt (0x00200).Ó
A DSI exception is never generated by hardware, but software may
branch to this location because of an data TLB error or miss exception.
See Section 7.1.2.3, ÒDSI Exception (0x00300).Ó
An ISI exception is never generated by the hardware, but software may
branch to this location because of an implementation-speciÞc instruction
TLB error exception. See Section 7.1.2.4, ÒISI Exception (0x00400).Ó
See Section 7.1.2.5, ÒExternal Interrupt Exception (0x00500).Ó
Alignment exceptions result from the following conditions:
¥ The operand of a load/store multiple is not word-aligned.
¥ The operand of a lwarx or stwcx. is not word-aligned.
¥ The operand of a load/store instruction is not naturally aligned when
MSR[LE] = 1.
¥ Trying to execute a multiple/string instruction when MSR[LE] = 1.
See Section 7.1.2.3, ÒDSI Exception (0x00300).Ó
The MPC860 cannot generate a ßoating-point exception type exception.
See Section 7.1.2.7, ÒProgram Exception (0x00700).Ó An
implementation-speciÞc software emulation exception is generated
instead of an illegal instruction type program exception. A privileged
instruction program exception is generated for an on-core valid SPR Þeld
or any SPR encoded as an external SPR if SPR[0] = 1 and MSR[PR] =
1, as well as for attempts to execute supervisor-level instructions when
MSR[PR] = 1. See Table 6-11.
MPC860 PowerQUICC UserÕs Manual
Description
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