Motorola MPC860 PowerQUICC User Manual page 182

Part II. PowerPC Microprocessor Module
aligned in either endian mode, an implementation may yield boundedly-undeÞned results
instead of causing an alignment exception. For all other cases listed above, an
implementation may execute the instruction correctly instead of causing an alignment
exception.
The register settings for alignment exceptions are shown in Table 7-7.
Table 7-7. Register Settings after an Alignment Exception
Register
SRR0 Set to the effective address of the instruction that caused the exception.
SRR1 0
1Ð4
5Ð9
10Ð15
16Ð31
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0
ILE Ñ
EE 0
PR 0
DSISR 0Ð14 Cleared
15Ð16 For instructions that use register indirect with index addressingÑset to bits 29Ð30 of the
instruction encoding.
For instructions that use register indirect with immediate index addressingÑcleared
17 For instructions that use register indirect with index addressingÑset to bit 25 of the instruction
encoding.
For instructions that use register indirect with immediate index addressingÑ set to bit 5 of the
instruction encoding.
18Ð21 For instructions that use register indirect with index addressingÑset to bits 21Ð24 of the
instruction encoding.
For instructions that use register indirect with immediate index addressingÑset to bits 1Ð4 of the
instruction encoding.
22Ð26 Set to bits 6Ð10 (identifying either the source or destination) of the instruction encoding.
UndeÞned for dcbz.
27Ð31 Set to bits 11Ð15 of the instruction encoding (rA) for update-form instructions
Set to either bits 11Ð15 of the instruction encoding or to any register number not in the range of
registers loaded by a valid form instruction for lmw, lswi, and lswx instructions. Otherwise
undeÞned.
If there is no corresponding instruction, no alternative value can be speciÞed.
DAR Set to the EA of the data access as computed by the instruction causing the alignment exception.
The architecture does not support the use of a misaligned EA by load/store with reservation
instructions. If one of these instructions speciÞes a misaligned EA, the exception handler
should not emulate the instruction but should treat the occurrence as a programming error.
7.1.2.6.1 Integer Alignment Exceptions
Operations that are not naturally aligned may suffer performance degradation, depending
on the processor design, the type of operation, the boundaries crossed, and the mode that
the processor is in during execution. More speciÞcally, these operations may either cause
7-8
Setting Description
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
FP 0
ME Ñ
SE 0
BE 0
MPC860 PowerQUICC UserÕs Manual
IP Ñ LE
IR 0
DR 0
RI 0
Set to value of ILE
MOTOROLA