Motorola MPC860 PowerQUICC User Manual page 310

Part III. Configuration
¥ External soft reset
¥ Internal soft reset
Ñ Debug port soft reset
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register reßects the last source to cause
a reset.
12.1.1 Power-On Reset
Power-on reset of the MPC860 is accomplished through the PORESET input signal. The
PORESET signal must be externally asserted following initial power-up, or when the
keep-alive power (KAPWR) voltage falls below the minimum required for proper system
operation in systems providing a power-down mode. When the PORESET signal is asserted
the MODCK bits are sampled and conÞgure SCCR[RTDIV] and SCCR[RTSEL]. The
phase-locked loop multiplication factor is conÞgured for default operation in the PLPRCR
register. When PORESET signal is negated, the MODCK values are sampled and internally
latched. To ensure proper operation, the PORESET signal should be asserted for a
minimum of 3 microseconds. After sampling the assertion of PORESET, the MPC860
enters the power-on reset state and stays there until both of the following events occur:
¥ The internal PLL enters the lock state and the system clock is active
¥ The PORESET signal is negated
After the negation of PORESET or PLL lock, the core enters the state of internal initiated
HRESET and continues driving the HRESET and SRESET signals for 512 clock cycles.
After 512 cycles elapse, the 860Õs conÞguration is sampled from the data signals and the
core stops internally asserting the HRESET and SRESET signals. To ensure prompt
negation external pull-up resistors should be provided to drive the HRESET and SRESET
signals high. After the HRESET and SRESET signals are internally negated, a 16-cycle
period passes before the presence of an external (hard/soft) reset will be sampled. Refer to
Section 12.3.1, ÒHard Reset,Ó for more information.
12.1.2 External Hard Reset
The hard reset (HRESET) signal is a bidirectional, active low, open-collector I/O signal.
The MPC860 can only sample an external assertion of HRESET if it occurs while the
MPC860 is not internally asserting HRESET. While HRESET is asserted, SRESET is also
asserted.
12.1.3 Internal Hard Reset
When the core initiates a hard reset it asserts the HRESET and SRESET signals for 512
cycles. After 512 clock cycles the data signals are sampled, initial conÞguration is
established, and the core stops driving the HRESET and SRESET signals. Following the
negation of HRESET and SRESET a 16-cycle period passes before an external hard or soft
reset will be sampled. Note that external pull-up resistors should be provided to drive the
12-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA