Motorola MPC860 PowerQUICC User Manual page 340

Part IV. Hardware Interface
Name Reset
BADDR30 Hi-Z
REG
BADDR[28Ð29] Hi-Z
AS Hi-Z
PA[15] Hi-Z
RXD1
3
4
RXD
PA[14] Hi-Z
TXD1
3
TXD4
PA[13] Hi-Z
RXD2
PA[12] Hi-Z
TXD2
PA[11] Hi-Z
L1TXDB
4
RXD3
13-14
Table 13-1. Signal Descriptions (Continued)
Number Type
K4 Output
M3 Output
M2
L3 Input
C18 Bidirectional General-Purpose I/O Port A Bit 15ÑBit 15 of the
D17 Bidirectional
(Optional:
Open-drain)
E17 Bidirectional General-Purpose I/O Port A Bit 13ÑBit 13 of the
F17 Bidirectional
(Optional:
Open-drain)
G16 Bidirectional
(Optional:
Open-drain)
MPC860 PowerQUICC UserÕs Manual
Description
Burst Address 30ÑThis output duplicates the value of A30
when the following is true:
¥ An internal master in the MPC860 initiates a transaction on
the external bus.
¥ An asynchronous external master initiates a transaction.
¥ A synchronous external master initiates a single beat
transaction.
The memory controller uses BADDR30 to increment the
address lines that connect to memory devices when a
synchronous external master or an internal master initiates a
burst transfer.
RegisterÑWhen an internal master initiates an access to a
slave under control of the PCMCIA interface, this signal
duplicates the value of TSIZ0/REG. When an external master
initiates an access, REG is output by the PCMCIA interface (if
it must handle the transfer) to indicate the space in the
PCMCIA card being accessed.
Burst AddressÑOutputs that duplicate A[28Ð29] values when
one of the following occurs:
¥ An internal master in the MPC860 initiates a transaction on
the external bus.
¥ An asynchronous external master initiates a transaction.
¥ A synchronous external master initiates a single beat
transaction.
The memory controller uses these signals to increment the
address lines that connect to memory devices when a
synchronous external or internal master starts a burst transfer.
Address StrobeÑInput driven by an external asynchronous
master to indicate a valid address on A[0Ð31]. The MPC860
memory controller synchronizes AS and controls the memory
device addressed under its control.
general-purpose I/O port A.
RXD1ÑReceive data input for SCC1.
3
RXD4 ÑReceive data input for SCC4.
General-Purpose I/O Port A Bit 14ÑBit 14 of the
general-purpose I/O port A.
TXD1ÑTransmit data output for SCC1.
3
TXD4 ÑTransmit data output for SCC4.
general-purpose I/O port A.
RXD2ÑReceive data input for SCC2.
General-Purpose I/O Port A Bit 12ÑBit 12 of the
general-purpose I/O port A.
TXD2ÑTransmit data output for SCC2.
General-Purpose I/O Port A Bit 11ÑBit 11 of the
general-purpose I/O port A.
L1TXDBÑTransmit data output for the serial interface TDMb.
4
RXD3 ÑReceive data input for SCC3.
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