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Chapter 8
Instruction and Data Caches
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80
The MPC860 contains separate 4-Kbyte, two-way set associative instruction and data
caches to allow rapid core access to instructions and data. This chapter describes the
organization of the on-chip instruction and data caches, cache control, various cache
operations, and the interaction between the caches, the load/store unit (LSU), the
instruction sequencer, and the system interface unit (SIU).
The MPC860 cache implementation has the following characteristics:
¥ There are two separate 4-Kbyte instruction and data caches (Harvard architecture).
¥ Both instruction and data caches are two-way set associative.
¥ The caches implement a least-recently-used (LRU) replacement algorithm within
each set.
¥ The cache directories are physically addressed. The physical (real) address tag is
stored in the cache directory.
¥ Both the instruction and data caches have 16-byte cache blocks. A cache block is the
block of memory that a coherency state describes, also referred to as a cache line.
¥ Two state bits for each data cache block allow encoding for three states:
Ñ ModiÞed-valid (sometimes called ÔmodiÞedÕ)
Ñ UnmodiÞed-valid (sometimes called ÔexclusiveÕ)
Ñ Invalid
¥ A single state bit for each instruction cache block allows encoding for two possible
states:
Ñ Valid
Ñ Invalid
¥ Both caches can be disabled, invalidated, or locked by issuing commands to their
respective cache control registers, special-purpose registers (SPRs) speciÞc to the
MPC860. See Section 8.3, ÒCache Control Registers,Ó for more information.
¥ Individual cache blocks can be locked so that frequently accessed instructions
and/or data are guaranteed to be resident in the respective cache.
On a cache miss, the MPC860Õs cache blocks are Þlled in 16-byte bursts. The burst Þll is
MOTOROLA
Chapter 8. Instruction and Data Caches
8-1
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