Motorola MPC860 PowerQUICC User Manual page 577

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Table 20-7. IDMA BD Status and Control Bits (Continued)
Bits
Name
3
I
Interrupt. Enable the maskable auxiliary-done (AD) interrupt.
0 IDSR[AD] is not ßagged after this BD is processed.
1 IDSR[AD] is ßagged after this BD is processed.
4
L
Last. Marks the end of a buffer chain and enables the maskable DONE interrupt.
0 Not the last BD of a buffer chain.
1 Last BD of a buffer chain. When the transfer count is exhausted, IDSR[DONE] is ßagged,
regardless of the I bit.
5
Ñ
Reserved
6
CM
Continuous mode. Selects buffer-chaining or auto-buffering; see Section 20.3.4.2, ÒAuto-Buffering
and Buffer-Chaining.Ó
0 Normal mode (buffer-chaining). The CP clears the V bit after this descriptor is processed.
1 Continuous mode (auto-buffering). The CP does not clear the V bit after this descriptor is
processed.
7Ð15
Ñ
Reserved
20.3.4.1 Function Code RegistersÑSFCR and DFCR
The user programs an IDMA channelÕs source and destination function code registers
(SFCR and DFCR) with separate 3-bit function codes to tag the channelÕs source and
destination accesses. The function code registers also determine the byte-ordering
convention. Figure 20-9 shows the register format.
Bit
0
Field
Addr
Figure 20-9. Function Code RegistersÑSFCR and DFCR
Table 20-8 describes the function code register bit settings.
Table 20-8. SFCR and DFCR Field Descriptions
Bits
Name
0Ð2
Ñ
Reserved. Should be cleared.
3Ð4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD. See Appendix A, ÒByte Ordering.Ó
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5Ð7
AT[1Ð3] Address type 1Ð3. Holds the function code for an IDMA channel memory access. Note AT[0] is
driven high to identify the access as a DMA type. Note that for the last IDMA cycle, the terminal
count code AT[0Ð3] = 0xF replaces the user-deÞned function code signaling the end of transfer to
the peripheral.
MOTOROLA
1
2
Ñ
DFCR is at offset 0x02. SFCR is at offset 0x03.
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
Description
3
4
BO
Description
5
6
AT[1Ð3]
20-11
7

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