Motorola MPC860 PowerQUICC User Manual page 613

Bit 0
Field CSRRa
Reset
R/W
Addr
Table 21-7 describes the SICMR Þelds.
Bits Name
0, 2 CSRR Change shadow RAM for TDMx receiver/transmitter. Set by the user; cleared by the SI when the
swap completes.
1, 3 CSRT
0 The shadow RAM is invalid. The shadow RAM can be written to program a new routing.
1 The shadow RAM is valid. The SI swaps the RAMs, taking the new routing from the shadow RAM.
4Ð7 Ñ Reserved, should be cleared.
21.2.4.5 SI Status Register (SISTR)
The SI status register (SISTR) indicates which part of the SI RAM is the current-route
RAM. The value of SISTR is valid only when the corresponding SICMR bit is clear.
Bit 0
Field CRORa CROTa
Reset
R/W
Addr
Table 21-8 describes the SISTR Þelds.
Bits Name
0 CRORa Address of the current route of TDMa receiver.
0 Address 0Ð127 when SIGMR[RDM] = 01.
Address 0Ð63 when SIGMR[RDM] = 11.
1 Address 128Ð255 when SIGMR[RDM] = 01.
Address 64Ð127 when SIGMR[RDM] = 11.
1 CROTa Address of the current route of TDMa transmitter.
0 Address 256Ð383 when SIGMR[RDM] = 01.
Address 256Ð319 when SIGMR[RDM] = 11.
1 Address 384Ð511 when SIGMR[RDM] = 01.
Address 320Ð383 when SIGMR[RDM] = 11.
MOTOROLA
1 2
CSRTa CSRRb
Figure 21-21. SI Command Register (SICMR)
Table 21-7. SICMR Field Descriptions
1 2
CRORb CROTb
Figure 21-22. SI Status Register (SISTR)
Table 21-8. SISTR Field Descriptions
Chapter 21. Serial Interface
Part V. The Communications Processor Module
3 4
CSRTb
0
R/W
0xAE7
Description
3 4
0
R
OxAE6
Description
5 6
Ñ
5 6
Ñ
7
7
21-25