Motorola MPC860 PowerQUICC User Manual page 439

Table 16-4. ORx Field Descriptions (Continued)
Bits Name
29 TRLX Timing relaxed (GPCM only)
0 Timing is not relaxed.
1 In addition to the timing parameters programmed in other ORx Þelds, timing is further relaxed. See
the effect of TRLX in Table 16-11. TRLX also doubles the wait-states programmed in SCY.
30 EHTR Extended hold time on read. (GPCM only)
0 Timing is deÞned by the memory controller.
1 After a read from the current bank, an additional clock cycle is inserted before the memory
controller responds to a write or read to another bank.
31 Ñ Reserved, should be cleared.
16.4.3 Memory Status Register (MSTAT)
The memory status register (MSTAT) reports parity and write-protect errors encountered
during an external bus access initiated by the memory controller. To clear a speciÞc bit,
write a one to it (writing zero has no effect).
Bit 0 1
Field PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 WPER
Reset
R/W
Addr
Figure 16-9. Memory Status Register (MSTAT)
Table 16-5 describes MSTAT Þelds.
Bits Name
0Ð7 PERx Parity error bank 0Ð7. Set when a parity error is detected during a read cycle to this bank initiated
by the memory controller.
8 WPER Write-protection error. Set when a write-protect error occurs on a write cycle to a write-protected
bank deÞned by BRx[WP].
9Ð15 Ñ Reserved, should be cleared.
16.4.4 Machine A Mode Register/
The machine x mode register (MAMR and MBMR) contain the conÞguration for UPMA
and UPMB, respectively. See Figure 16-1.
MOTOROLA
2 3 4 5
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x178
Table 16-5. MSTAT Field Descriptions
Chapter 16. Memory Controller
Description
6 7 8 9
R/W
Description
achine B Mode Registers (MxMR)
M
Part IV. Hardware Interface
10 11 12 13 14
Ñ
16-13
15