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Table 9-17. MI_RAM0 Field Descriptions (Continued)
Bits
Name
28
SFP
Supervisor (supervisor) fetch permission
0 Subpage 0 (Address[20Ð21] = 00) Supervisor fetch is not permitted
1 Subpage 0 (Address[20Ð21] = 00) Supervisor fetch is permitted
29
0 Subpage 1 (Address[20Ð21] = 01) Supervisor fetch is not permitted
1 Subpage 1 (Address[20Ð21] = 01) Supervisor fetch is permitted
30
0 Subpage 2 (Address[20Ð21] = 10) Supervisor fetch is not permitted
1 Subpage 2 (Address[20Ð21] = 10) Supervisor fetch is permitted
31
0 Subpage 3 (Address[20Ð21] = 11) Supervisor fetch is not permitted
1 Subpage 3 (Address[20Ð21] = 11) Supervisor fetch is permitted
9.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1)
The IMMU RAM entry read register 1 (MI_RAM1), shown in Figure 9-19, contains the
protection mode information of the entry indexed by MI_CTR[ITLB_INDX]. This register
is updated only when MI_CAM is written to.
Bit
0
1
2
Field
Reset
R/W
Bit
16
17
18
Field
Reset
R/W
SPR
Figure 9-19. IMMU RAM Entry Read Register 1 (MI_RAM1)
Table 9-18 describes MI_RAM1 Þelds.
Bits
Name
0Ð25
Ñ
26
UFP
27
28
29
MOTOROLA
3
4
5
6
19
20
21
22
Ñ
0
Table 9-18. MI_RAM1 Field Descriptions
Reserved
User fetch permission
0 Subpage 0 (Address[20Ð21] = 00) User fetch is not permitted
1 Subpage 0 (Address[20Ð21] = 00) User fetch is permitted
0 Subpage 1 (Address[20Ð21] = 01) User fetch is not permitted
1 Subpage 1 (Address[20Ð21] = 01) User fetch is permitted
0 Subpage 2 (Address[20Ð21] = 10) User fetch is not permitted
1 Subpage 2 (Address[20Ð21] = 10) User fetch is permitted
0 Subpage 3 (Address[20Ð21] = 11) User fetch is not permitted
1 Subpage 3 (Address[20Ð21] = 11) User fetch is permitted
Chapter 9. Memory Management Unit (MMU)
Part II. PowerPC Microprocessor Module
Description
7
8
9
10
Ñ
0
R
23
24
25
26
R
818
Description
11
12
13
14
27
28
29
30
UFP
PV
Ñ
Ñ
9-27
15
31
G
Ñ
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