Motorola MPC860 PowerQUICC User Manual page 907

CPM sub-blocks with multiple interrupting events can be masked individually by
programming a mask register within that block (such as the SMC UART register (SMCM),
described in Section 30.3.12, ÒSMC UART Event Register (SMCE)/Mask Register
(SMCM)Ó). Table 35-2 shows the interrupt sources that have multiple interrupting events.
Figure 35-2 shows masking using the SMC sub-block.
SMCEx 3
¥ ¥ ¥
BRK
The following procedure prevents possible interrupt errors when modifying mask registers,
such as the CIMR, SCCM, SMCM, or any other CPM interrupt mask:
1. Clear MSR[EE]. (Disable external interrupts to the core.)
2. Modify the mask register.
3. Set MSR[EE]. (Enable external interrupts to the core.)
This mask modiÞcation procedure ensures that an already pending interrupt is not masked
before being serviced. Masking a pending interrupt causes the interrupt error vector (see
Table 35-2) to be issued if no other valid CPM interrupts are pending. (The error vector
cannot be masked.)
35.4 Generating and Calculating Interrupt Vectors
Unmasked CPM interrupts are presented to the core in order of priority. The core responds
to an interrupt request by setting CIVR[IACK]. The CPIC passes the Þve low-order bits of
the vector corresponding to the highest priority, unmasked, pending CPM interrupt in
CIVR[VN]. These encodings are shown in Table 35-2.
MOTOROLA
4 5 6 7
Ð BSY TX RX
SMCx Interrupt to CPIC
Figure 35-2. Interrupt Request Masking
Chapter 35. CPM Interrupt Controller
Part V. The Communications Processor Module
SMCMx 3 4 5
¥ ¥ ¥
BRK Ð BSY
6 7
TX RX
35-5