Table of Contents
Advertisement
Part II. PowerPC Microprocessor Module
¥ Supports up to 16 virtual address spaces
¥ Supports 16 access protection groups (group protection overrides page protection)
¥ Separate 32-entry, fully-associative data translation lookaside buffer (DTLB) and
instruction TLB (ITLB) with the following features:
Ñ Implementation-speciÞc exceptionsÑITLB and DTLB miss exceptions, ITLB
and DTLB error exceptions
Ñ Supports PowerPC tlbie and tlbia instructions. The tlbsync instruction, which is
optional to PowerPC implementations, is not supported and is treated as a no-op.
Ñ Software tablewalk updates supported by DTLB and ITLB miss exceptions and
SPRs
Ñ Each entry can be programmed to match user or supervisor accesses or both.
Ñ Four entries in each TLB can optionally be locked to ensure fast translation for
selected regions.
¥ High performance
Ñ 1 clock (zero wait state) access for a data cache hit and for an instruction cache
hit when the access is from the same page as the previous access
Ñ 1 clock penalty for other TLB hit instruction accesses
¥ Low power consumption
9.2 PowerPC Architecture Compliance
The MPC860 core complies largely with the MMU as it is deÞned by the OEA, with the
following differences:
¥ The MPC860 does not implement the following PowerPC features:
Ñ Block-address translation
Ñ The optional direct-store functionality
Ñ The memory coherency attribute
¥ The MPC860 supports the following additional features not deÞned by the PowerPC
architecture:
Ñ Variable page sizes. The OEA deÞnes 4-Kbyte pages only
Ñ Programmable defaults for write-through and cache-inhibited memory attributes
when translation is disabled.
Ñ Additional registers and exceptions for handling table walks in software.
Note that although the MPC860 does not deÞne segment registers as they are deÞned by the
OEA, the concept of segment is retained as the memory space accessible to the level-one
table descriptors.
9-2
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Advertisement
Table of Contents
