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15.5.1 Normal High Mode
Normal high mode is the default mode of the MPC860 . In this mode, the GCLKx
frequency is determined by SCCR[DFNH], and all modules of the MPC860 are enabled.
For more information about SCCR[DFNH], refer to Section 15.3.1.1, ÒThe Internal
General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2).
Normal high mode is selected if PLPRCR[CSRC]=0 and PLPRCR[LPM]=00, or if an
enabled event has caused an exit from another low-power mode.
15.5.2 Normal Low Mode
Normal low mode takes advantages of the low-power dividers for GCLKx to enable full
functionality of the MPC860 , but at a lower frequency so that power consumption is
reduced. The low-power dividers allow the system to reduce and restore the operating
frequencies of different sections of the MPC860 without losing the SPLL lock. This mode
is sometimes referred to as slow-go or low gear mode.
Normal low mode is selected if PLPRCR[CSRC]=1 and PLPRCR[LPM]=00. In normal
low mode, the GCLKx frequency is determined by SCCR[DFNL]. For more information
about SCCR[DFNL], refer to Section 15.3.1.1, ÒThe Internal General System Clocks
(GCLK1C, GCLK2C, GCLK1, GCLK2). Note also that PLPRCR[TMIST] should be
cleared before entering normal low mode; for more information, see Section 15.5.8,
ÒTMIST: Facilitating Nesting of SIU Timer Interrupts.
Normal low mode can be entered at any time, and the frequency of operation of normal low
mode can be changed dynamically. This is controlled by PLPRCR[CSRC] and
SCCR[DFNL]. The effects of changes to these bits occur immediately.
The following events will cause the MPC860 to leave normal low mode and enter normal
high mode:
¥ A pending interrupt from the interrupt controller occurs. This option is maskable
with SCCR[PRQEN]. These interrupts include all internal and external interrupt
sources, if enabled.
¥ Software-initiation, by writing MSR[POW] = 0. This option is maskable with
SCCR[PRQEN].
¥ The communications processor (CP) has a service request from a peripheral (e.g.
SCC, SMC, etc.). This option is maskable with SCCR[CRQEN].
15.5.3 Doze High Mode
When software initiates the doze high mode, software processing on the core suspends. The
GCLKxC clocks to the core, MMUs, and caches are disabled. However, the CPM and SIU
continue to function as normal.
Doze
high
mode
PLPRCR[LPM]=01. In doze high mode, the GCLKx frequency is determined by
MOTOROLA
is
selected
if
PLPRCR[CSRC]=0,
Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
MSR[POW]=1,
and
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