Motorola MPC860 PowerQUICC User Manual page 266

Part II. PowerPC Microprocessor Module
10.1.5 A Full Completion Queue
Figure 10-6 shows stalls due to a full CQ. Here, the CQ is full from executing sub, addic,
and and. It takes one more bubble from the load writeback to allow further issue while the
CQ retires sub, addic, and and.
lwz r12,64 (SP)
sub r5,r5,3
addic r4,r14,1
and r3,r4.r5
xor r4,r3,r5
ori r7,r8,1
GCLK1
Fetch lwz
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
10.1.6 Branch Instruction Handling
In Figure 10-7 the lwz instruction accesses internal memory with one wait state. The IQ and
parallel operation of the BPU allows the two bubbles caused by the bl issue and execution
to overlap the two bubbles caused by the load. Issuing bl causes a bubble because it does
no work.
lwz
r12,64 (SP)
sub
r3,r12,3
addic
r4,r14,1
bl
func
...
func:
mulli
r5,r3,3
addi
r4,3(r0)
10-4
sub addic
lwz sub addic
lwz sub
lwz
lwz
Figure 10-6. Full Completion Queue Timing
MPC860 PowerQUICC UserÕs Manual
and xor ori
and xor
addic and Bubble
sub addic and
lwz
lwz
Bubble xor
xor
lwz
lwz
MOTOROLA