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Physical memory. The actual memory that can be accessed through the
Pipelining. A technique that breaks operations, such as instruction
Precise exceptions. A category of exception for which the pipeline can be
Primary opcode. The most-signiÞcant 6 bits (bits 0Ð5) of the instruction
Protection boundary. A boundary between protection domains.
Protection domain. A protection domain is a segment, a virtual page, a BAT
Q
Quad word. A group of 16 contiguous locations starting at an address
R
rA. The rA instruction Þeld is used to specify a GPR to be used as a source
rB. The rB instruction Þeld is used to specify a GPR to be used as a source.
rD. The rD instruction Þeld is used to specify a GPR to be used as a
rS. The rS instruction Þeld is used to specify a GPR to be used as a source.
Real address mode. An MMU mode when no address translation is
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set,
Glossary--8
systemÕs memory bus.
processing or bus transactions, into smaller distinct stages or tenures
(respectively) so that a subsequent operation can begin before the
previous one has completed.
stopped so instructions that preceded the faulting instruction can
complete, and subsequent instructions can be ßushed and
redispatched after exception handling has completed. See Imprecise
exceptions.
encoding that identiÞes the type of instruction. See Secondary
opcode.
area, or a range of unmapped effective addresses. It is deÞned only
when the appropriate relocate bit in the MSR (IR or DR) is 1.
divisible by 16.
or destination.
destination.
performed and the effective address speciÞed is the same as the
physical address. The processorÕs MMU is operating in real address
mode if its ability to perform address translation has been disabled
through the MSR registers IR and/or DR bits.
updates the condition register (CR) to reßect the result of the
operation.
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
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