Table of Contents
Advertisement
Appendix A
Byte Ordering
A0
A0
The MPC860 supports three byte-ordering conventionsÑbig-endian (BE), true
little-endian (TLE), and PowerPCª architecture little-endian (PPC-LE). This chapter
describes each of the three endian modes. Chapter 3, ÒOperand Conventions,Ó in PowerPC
Microprocessor Family: The Programming Environments for 32-bit Microprocessors,
provides a general overview of byte ordering and describes byte ordering for PowerPC
microprocessors.
A.1 Byte Ordering Overview
For big-endian byte ordering, the most-signiÞcant byte (MSB) is stored at the lowest
address while the least-signiÞcant byte (LSB) is stored at the highest address. This is called
big-endian because the big end of the scalar comes Þrst in memory.
For true little-endian byte ordering, the LSB is stored at the lowest address while the MSB
is stored at the highest address. This is called true little-endian because the little end of the
scalar comes Þrst in memory.
For PowerPC little-endian byte ordering (also referred to as Ômunged little-endianÕ), the
address of data is modiÞed so that the memory structure appears little-endian to the
executing processor, when in fact, the byte ordering is big-endian. The address modiÞcation
is called ÔmungingÕ. Note that the term ÔmungingÕ is not deÞned or used in the PowerPC
architecture speciÞcation. However, the term is commonly used to describe address
modiÞcations. The byte ordering is called PowerPC little-endian because PowerPC
microprocessors use this method to operate in little-endian mode.
A.2 MPC860 Byte-Ordering Mechanisms
There are several byte-ordering mechanisms in the MPC860 that are controlled by
programmable parameters. The MSR[LE] and MSR[ILE] bits control a 3-bit address
modiÞer in the PowerPC core. The DC_CST[LES] bit controls a 2-bit address modiÞer in
the core and a 2-bit address modiÞer and byte lane swapper in the SIU. The FCR[BO] Þeld
2
of each peripheral (SCCs, SMCs, SPI, I
C, PIP, or IDMA) controls a 3-bit address modiÞer
in the SDMA. Table A-1 correlates the programmable parameters with the byte-ordering
modes of operation.
MOTOROLA
Appendix A. Byte Ordering
A-1
Advertisement
Table of Contents
