Motorola MPC860 PowerQUICC User Manual page 210

Part II. PowerPC Microprocessor Module
8.3.2.2.1 Data Cache Enable/Disable Commands
The data cache enable command (DC_CST[CMD] = 0b0010) is used to enable the data
cache; the data cache disable command (DC_CST[CMD] = 0b0100) is used to disable the
data cache. Neither of these commands has any error cases. The current state of the data
cache is available by reading the data cache enable status bit (DC_CST[DEN]).
When disabled, the MPC860 ignores the data cache state bits and operates as if all accesses
have caching-inhibited access attributes (that is, all accesses are propagated to the bus as
single-beat transactions). Disabling the data cache does not affect the data address
translation logic; MSR[DR] controls data address translation.
Note that the data cache is disabled at hard reset. Also, the data cache is automatically
disabled when a type 1 data cache error (see Table 8-6 for DC_CST[CCER1] conditions)
generates a machine check exception.
8.3.2.2.2 Data Cache Load & Lock Cache Block Command
The data cache load & lock cache block command (DC_CST[CMD] = 0b0110) is used to
lock critical data in the data cache. Locked cache blocks are not replaced during misses and
are not affected by invalidate commands.
To load & lock one or more cache blocks:
1. Read the DC_CST error type bits to clear them.
2. Write the address of the cache block to be locked to the DC_ADR register.
3. Write the load & lock cache block command (DC_CST[CMD] = 0b0110) to the
DC_CST register.
4. Repeat steps 2 and 3 to load & lock another cache block.
5. Read DC_CST[CCER2] to determine if the sequence completed without errors.
After the load & lock cache block command is written to the DC_CST register, the cache
checks if the block containing the byte addressed by DC_ADR[ADR] is in the cache (hit).
If it is in the cache, the block is locked and the command terminates with no exception. If
the block is not in the cache, a normal miss sequence is initiated (see Section 8.6, ÒData
Cache Operation,Ó for more information). After the addressed block is placed into the
cache, the block is locked.
The user must check DC_CST[CCER2] to determine if the load & lock cache block
operation completed without error. The error type bits in the DC_CST register are sticky,
thus allowing the user to perform a series of load & lock commands before checking the
termination status. These bits are set by the MPC860 and are cleared by software.
Note that the MPC860 considers all zero-wait-state devices on the internal bus as
caching-inhibited. For this reason, software should not perform load & lock operations
from these devices on the internal bus.
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