Table of Contents
Advertisement
CE=0
L1CLK
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
Figure 21-19. CE = 0 and FE Interaction with xFSD = 0
21.2.4.3 SI Clock Route Register (SICR)
The SI clock route register (SICR), shown in Figure 21-20, selects the SCC clock source
from one of four baud rate generators or an input from the bank of clock pins. The SICR
also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE.
MOTOROLA
Part V. The Communications Processor Module
The L1ST is Driven from Sync.
Data is Driven From Clock High.
Rx Sampled Here
L1ST is Driven from Clock Low.
Both the Data and L1ST from Sync
when Asserted during Clock High.
Both the Data and L1ST from the Clock
when Asserted during Clock Low.
Chapter 21. Serial Interface
xFSD=0
(FE=1)
(FE=1)
(FE=0)
(FE=0)
21-23
Advertisement
Table of Contents
