Motorola MPC860 PowerQUICC User Manual page 250

Part II. PowerPC Microprocessor Module
Table 9-14 describes M_CASID Þelds.
Bits Name
0Ð27 Ñ Reserved. Ignored on write. Returns 0 on read
28Ð31 CASID Current address space ID. Compared with ASID Þeld of a TLB entry to qualify a match
9.8.10 MMU Access Protection Registers (MI_AP/MD_AP)
The IMMU access protection register (MI_AP, SPR 786) contains the settings for the
access protection groups for the IMMU. The DMMU access protection register (MD_AP,
SPR 794) is identical. Both registers are shown in Figure 9-15.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field GP0 GP1 GP2 GP3 GP4 GP5
Reset
R/W
SPR
Figure 9-15. MMU Access Protection Registers (MI_AP/MD_AP)
MI_AP/MD_AP Þelds are described in Table 9-15.
Bits Name Domain Manager Mode (Mx_CTR[GPM] = 1)
0Ð1 GPx GP
00 No access
2Ð3
01 ClientÐaccess permission deÞned by page
protection bits
É
10 Reserved
11 ManagerÐfree access
30Ð31
9.8.11 MMU Tablewalk Special Register (M_TW)
The MMU tablewalk special register (M_TW), shown in Figure 9-16, is a scratch register
used by tablewalk exception handlers.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reset
R/W
SPR
Figure 9-16. MMU Tablewalk Special Register (M_TW)
9-24
Table 9-14. M_CASID Field Descriptions
GP6
786 (MI_AP); 794 (MD_AP)
Table 9-15. MI_AP/MD_AP Field Descriptions
MPC860 PowerQUICC UserÕs Manual
Description
GP7 GP8z GP9 GP10 GP11 GP12 GP13 GP14 GP15
Ñ
R/W
PowerPC Mode (Mx_CTR[GPM] = 0)
GP = Ks/Kp as deÞned by PowerPC architecture
00 All accesses are treated as supervisor
01 Access permission deÞned by page protection
bits
10 User and supervisor interpretation is swapped
11 All accesses are treated as user
Ñ
R/W
799
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