Motorola MPC860 PowerQUICC User Manual page 400

Part IV. Hardware Interface
oscclk
phase
comparator
feedback
clock
delay
The OSCCLK signal goes to the phase comparator that controls the direction in which the
charge pump drives the voltage across the external Þlter capacitor (XFC). Direction is based
on whether the feedback signal phase lags or leads the reference signal. The output of the
charge pump drives a voltage-controlled oscillator (VCO). The VCO output frequency
(VCOOUT) is divided down and fed back to the phase comparator to be compared with the
reference frequency (OSCCLK signal). The multiplication factor is programmable in the
PLPRCR[MF] between 1 and 4,096.
The minimum VCOOUT operating frequency of the SPLL is 15 MHz. This condition must
be maintained both by the reset conÞguration settings of the SPLL and at the Þnal operating
frequency of the SPLL.
The OSCCLK can be supplied by either a crystal or an external clock oscillator. Crystals
are typically much cheaper than clock oscillators; however, a clock oscillator has signiÞcant
design advantages over a crystal circuit in that clock oscillators are easier to work with,
resulting in faster design, debugging and production.
Furthermore, it should be noted that low-frequency crystals should not be used for the
source of OSCCLK if high-frequency SPLL operation is desired. This is because the
default startup multiplication factor of the SPLL requires a loop Þlter capacitor (XFC)
which is incompatible with the capacitor value required at the Þnal operating frequency. For
example, if a 50 MHz Þnal value was desired and a 32.768 KHz crystal was used, the XFC
range allowable by the default SPLL multiplication factor of 513 is 0.27 mF < XFC < 0.47
mF, whereas the Þnal SPLL multiplication factor of 1526 would require an XFC range of
0.79 mF < XFC < 1.40 mF.
15.2.2.1 SPLL Reset ConÞguration
While PORESET is asserted, the reset conÞguration of the SPLL is sampled on the
MODCK[1-2] pins. The SPLL immediately begins to use the multiplication factor
PLPRCR[MF] value and external clock source for OSCCLK determined by the sampled
MODCK[1-2] pin and attempts to achieve lock; therefore, the MODCK[1-2] signals should
15-6
XFC
up
charge
down
pump
VDDSYN / VSSSYN
multiplication factor
Figure 15-4. SPLL Block Diagram
MPC860 PowerQUICC UserÕs Manual
vcoout
VCO
PLPRCR[MF]
MOTOROLA