Motorola MPC860 PowerQUICC User Manual page 573

Table 20-4. IDMA Parameter RAM Memory Map (Continued)
0x08 DAPR
0x0C IBPTR Hword
0x0E WRITE_SP Hword
0x10 S_BYTE_C
0x14 D_BYTE_C
0x18 S_STATE
0x1C ITEMP 4 Words Temp data storage
0x2C SR_MEM
0x30 READ_SP Hword
0x32 Ñ Hword
0x34 Ñ Hword
0x36 Ñ Hword
0x38 D_STATE
¥ Notes: Boldfaced items must be initialized by the user before enabling an IDMA channel. The remaining
parameters are used by the CP only.
1
IDMA1 base = IMMR + 0x3CC0
IDMA2 base = IMMR + 0x3DC0
20.3.3 IDMA Registers
Each IDMA channel has a DMA channel mode register (DCMR), an IDMA status register
(IDSR) and corresponding mask register (IDMR) that contain global channel parameters.
20.3.3.1 DMA Channel Mode Registers (DCMR)
Located in each IDMAÕs parameter RAM, the DMA channel mode registers (DCMR)
conÞgure the peripheral port size, the source and destination type of the transfer, and the
address mode (cycle mode) of the IDMA channels. Figure 20-5 shows the register format.
Bit 0 1 2
Field
Reset
R/W
Addr
Figure 20-5. DMA Channel Mode Register (DCMR)
MOTOROLA
Word Destination data pointer (internal-use). Points to the next destination byte to be
written. The CP initializes DAPR to the BDÕs destination buffer pointer, and
increments it automatically if the destination is memory (DCMR[S/D] = 0b0x).
Current IDMA BD pointer. If the IDMA channel is idle, IBPTR points to the next
valid BD in the table. After a reset, or when the end (wrap bit) of the BD table is
reached, the CP wraps IBPTR back to IBASE.
Internal-use
Word Internal source byte count
Word Internal destination byte count
Word Internal state
Word Data storage for peripheral write
Internal-use
Difference between source and destination residue
Temp storage address pointer
SR_MEM byte count
Word Reserved. Internal state used by CP
3 4 5 6
Ñ
0
R
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
7 8 9 10
IDMAx Base + 0x02
11 12 13 14
SIZE S/D
0 0
R/W R/W R/W
20-7
15
SC
0