Motorola MPC860 PowerQUICC User Manual page 722

Part V. The Communications Processor Module
Table 26-7 describes SCCE/SCCM Þelds.
Bits Name
0Ð2 Ñ Reserved, should be cleared.
3 GLR Glitch on Rx. Set when the SCC Þnds a Rx clock glitch.
4 GLT Glitch on Tx. Set when the SCC Þnds a Tx clock glitch.
5Ð6 Ñ Reserved, should be cleared.
7 IDL Idle sequence status changed. Set when serial line status changes. Real-time status can be read in
SCCS[ID].
8 Ñ Reserved, should be cleared.
9 TXE Tx error. Set when an error occurs on the transmitter channel.
10 BRKE Break end. Marks the end of a break sequenceÑset when an idle bit is detected after a break sequence.
11 BRKS Break start. Set when the Þrst break character of a break sequence is received. Only one BRKS event
occurs per break sequence, no matter the length of the sequence.
12 RXF Rx frame. Set when the number of frames speciÞed in RFTHR are received. RXF is set no sooner than
when the midpoint of the closing ßagÕs stop bit arrives.
13 BSY Busy condition. Set when a frame is received and discarded due to a buffer shortage.
14 TXB Transmit buffer. Set when a buffer with TxBD[I] set is sent on the channel, not before the last bit of the
closing ßag begins its transmission if the buffer is the last one in the frame. Otherwise, TXB is set after
the last byte of the buffer is written to the Tx FIFO.
15 RXB Rx buffer. Set when a buffer with RxBD[I] set and RxBD[L] cleared is received over the channel.
26.13.2 SCC Asynchronous HDLC Status Register (SCCS)
The SCC asynchronous HDLC status register (SCCS), shown in Figure 26-5, monitors the
real-time status of RXD. The real-time status of CTS and CD is part of the port C parallel
I/O.
Bit 0
Field
Reset
R/W
Addr
Figure 26-5. SCC Status Register for Asynchronous HDLC Mode (SCCS)
Table 26-8 describes asynchronous HDLC SCCS Þelds.
26-10
Table 26-7. SCCE/SCCM Field Descriptions
1 2
0000_0000_0000_0000
0xA17 (SCCS1), 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4)
MPC860 PowerQUICC UserÕs Manual
Description
3 4
Ñ
R
5 6 7
ID
MOTOROLA