Motorola MPC860 PowerQUICC User Manual page 830

Part V. The Communications Processor Module
Figure 31-2. Single-Master/Multi-Slave Configuration
To start exchanging data, the core writes the data to be sent into a buffer, conÞgures a TxBD
with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets SPCOM[STR]
in the SPI command register to start sending data, which starts once the SDMA channel
loads the Tx FIFO with data.
The SPI then generates programmable clock pulses on SPICLK for each character and
simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data
is written into a Rx buffer using the next available RxBD. The SPI keeps sending and
receiving characters until the whole buffer is sent or an error occurs. The CPM then clears
TxBD[R] and RxBD[E] and issues a maskable interrupt to the CPM interrupt controller
(CPIC).
When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting
without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD
is processed after data from the current buffer is sent. Typically there is no delay on
SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current
buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer
is not full; therefore, Rx buffers need not be the same length as Tx buffers.
31-4
MPC860
SPIMOSI
SPIMISO
SPICLK
Master SPI
The SPISEL
decoder can be
either internal or
external logic.
MPC860 PowerQUICC UserÕs Manual
Slave 0
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 1
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 2
SPIMOSI
SPIMISO
SPICLK
SPISEL
MOTOROLA