Table of Contents
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Byte-reverse instructions, D-22
Byte-select signals, 16-39
C
Cache
cache block
memory control instructions, 6-21
cache block, definition, 8-1
cache blocks, locked, 8-10
cache control instructions, 8-18
cache control registers, 8-6
cache line, definition, 8-1
data cache
atomic memory references, 8-28
caching-inhibited data accesses, 8-27
copyback buffer, 8-14
DC_CST commands, 8-15
debug mode, 8-29
debugger, software monitor, 8-30
disable command, 8-16
enable command, 8-16
flush cache block command, 8-17
invalidate all command, 8-17
load & lock cache block command, 8-16
load hit, 8-25
memory coherency, 8-6
operations, 8-24
organization, 8-5
read miss, 8-25
reading tags, 8-14
registers, 8-11
snooping, 8-6
store hit (write-back mode), 8-26
store hit (write-through mode), 8-26
store miss (write-back mode), 8-27
store miss (write-through mode), 8-26
unlock all commands, 8-17
unlock cache block command, 8-17
write-back mode, 8-26
write-through mode, 8-26
debug support, 8-29
initialization after reset, 8-29
instruction cache
block buffer, 8-21
burst buffer, 8-21
cache hit, 8-22
cache miss, 8-22
caching-inhibited instruction fetch, 8-23
data path, 8-21
debug mode, 8-29
debugger, software monitor, 8-30
disable commands, 8-9
enable commands, 8-9
IC_CST commands, 8-9
Index--2
INDEX
Cache management instructions, D-26
Cascaded mode, 18-7
Centronics interface, see Parallel interface port
Checkstop reset, 12-3
Chip-select machine, 16-18
Chip-select signals
CLAMP instruction, 38-7
Clock dividers, low-power, 15-10
Clock glitch detection, 22-25
Clocks, 15-9
Commands
Communcations processor module (CPM)
MPC860 PowerQUICC UserÕs Manual
instruction fetching, 8-23
instruction sequencer, 8-2, 8-20
invalidate all command, 8-11
load & lock cache block commands, 8-10
memory coherency, 8-4
operations, 8-20
organization, 8-2
read command, 8-9
reading data, 8-8
reading tags, 8-9
registers, 8-6
snooping, 8-4, 8-24
stream hits, 8-22
unlock all command, 8-11
unlock cache block command, 8-11
updating code, 8-24
instructions, D-26
intruction cache
hits under misses, 8-22
locked cache blocks, 8-10
memory/cache access attributes, 8-18
write-back mode, 8-26
write-through mode, 8-26
Signals
chip-select signals, 16-39
baud rate generator, 15-14
development port serial communications clock
mode, 37-28
2
I
C controller clocking, 32-2
overview, 15-1
SCC clock glitch detection, 22-25
serial clocking (peak rate limitation), B-1
synchronization clocks, 15-14
SET TIMER, 19-13
CPM interrupt controller
calculating interrupt vectors, 35-5
features, 35-1
generating interrupt vectors, 35-5
highest priority interrupt, 35-4
interrupt handler examples, 35-10
masking interrupt sources, 35-4
nested interrupts, 35-4
MOTOROLA
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