Motorola MPC860 PowerQUICC User Manual page 222

Part II. PowerPC Microprocessor Module
have, that those blocks have been ßushed from the cache. Whenever the memory/cache
attributes of any memory region are changed (for example, from caching-allowed to
caching-inhibited), it is critical that the cache contents reßect the new attributes. Therefore,
when changing memory region attributes (in the MMU) the user must perform the
procedures described in Section 8.5.5, ÒUpdating Code And Memory Region Attributes.Ó.
8.6.6 Atomic Memory References
The PowerPC architecture deÞnes the Load Word and Reserve Indexed (lwarx) and the
Store Word Conditional Indexed (stwcx.) instructions to provide an atomic update function
for a single, aligned word of memory. These instructions can be used to develop a rich set
of multiprocessor synchronization primitives. For detailed information on these
instructions, refer to Section 6.2.4.6, ÒMemory Synchronization InstructionsÑUISA,Ó in
this book and Chapter 8, ÒInstruction Set,Ó in The Programming Environments Manual.
The lwarx instruction performs a load word from memory operation and creates a
reservation for the 16-byte section of memory that contains the accessed word. The
reservation granularity is 16 bytes. The lwarx instruction makes a nonspeciÞc reservation
with respect to the executing processor and a speciÞc reservation with respect to other
masters. This means that any subsequent stwcx. executed by the same processor, regardless
of address, will cancel the reservation. Also, any bus write operation from another
processor to an address that matches the reservation address will cancel the reservation.
The stwcx. instruction does not check the reservation for a matching address. The stwcx.
instruction is only required to determine whether a reservation exists. The stwcx.
instruction performs a store word operation only if the reservation exists. If the reservation
has been cancelled for any reason, then the stwcx. instruction fails and clears the CR0[EQ]
bit in the condition register. The architectural intent is to follow the lwarx/stwcx.
instruction pair with a conditional branch which checks to see whether the stwcx.
instruction failed.
Note that atomic memory references constructed using lwarx/stwcx. instructions depend
on the presence of a coherent memory system for correct operation. These instructions
should not be expected to provide atomic access to noncoherent memory. Since the
MPC860 does not snoop external bus activity, provision is made to cancel a reservation
inside the MPC860 by using the CR and KR input signals. The state of the reservation is
always presented onto the RSV output signal. This can be used by external agents to
determine when an internal condition has caused a change in the reservation state. See
Section 14.4.9, ÒMemory Reservation,Ó for more information. Internal to the MPC860, the
data cache has snoop logic to monitor the internal bus for communication processor module
(CPM) accesses of the address associated with the last lwarx instruction.
If a memory region is marked caching-allowed, the MPC860 assumes that it is the single
master in the system to that region. If a caching-allowed lwarx or stwcx. access misses in
the data cache, the transaction on the internal and external buses do not have a reservation.
8-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA