Table of Contents
Advertisement
Functionality
Memory
The MPC860 interprets cache control instructions as if they pertain only to the MPC860 cache.
control
These instructions do not broadcast. Any bus activity caused by these instructions results from an
instructions
operation performed on the MPC860 cache and not because of the instruction itself.
¥ Instruction Cache Block Invalidate (icbi)ÑThe MMU translates the EA and the associated
instruction cache block is invalidated if hit.
¥ Instruction Synchronize (isync)ÑThe isync instruction waits for all previous instructions to
complete and then discards any prefetched instructions, causing subsequent instructions to be
fetched or refetched from memory and executed.
¥ Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)ÑThe appropriate
cache block is checked for a hit. If it is a miss, the instruction is treated as a regular miss, except
that bus error does not cause an exception. If no error occurs, the cache is updated.
¥ Data Cache Block Set to Zero (dcbz)ÑExecutes as deÞned in the VEA.
¥ Data Cache Block Store (dcbst)ÑExecutes as deÞned in the VEA.
¥ Data Cache Block Invalidate (dcbi)ÑThe MMU translates the EA and the associative data cache
block is invalidated if hit.
¥ Data Cache Block Flush (dcbf)ÑExecutes as deÞned in the VEA.
¥ Enforce In-Order Execution of I/O (eieio)ÑWhen executing an eieio instruction, the LSU waits for
previous accesses to terminate before beginning accesses associated with load/store instructions
after the eieio instruction.
Time base
The time base functions as deÞned by the VEA and supports an additional implementation-speciÞc
exception. The time base is described in Chapter 11, ÒSystem Interface Unit,Ó and in Chapter 15,
ÒClocks and Power Control.Ó
Table 4-5 summarizes MPC860 features with respect to the OEA deÞnition.
Functionality
Machine state
The ßoating-point exception mode (bits FE0 and FE1) is ignored by the MPC860. The IP bit initial
register
state after reset is set as programmed by the reset conÞguration speciÞed in Section 7.1.2.1,
ÒSystem Reset Interrupt (0x00100).Ó
Processor
The value of the PVR registerÕs version Þeld is 0x0050. The value of the revision Þeld is 0x0000 and
version register
it is incremented each time the software distinguishes between the revisions.
Other OEA
The following registers are not implemented: SDR1, BAT registers, segment registers, and EAR
registers
Page size
The MPC860 differs from the OEA-deÞned memory management mode with respect to page sizes.
Page sizes are 4, 16, and 512 Kbytes, and 8 Mbytes with an optional subpage granularity of 1 Kbyte
for 4-Kbyte pages in a maximum physical memory size of 4 Gbytes. Neither ordinary or direct-store
segments are supported.
Address space
The MPC860 differs from the OEA-deÞned memory management model. SpeciÞcally, it does not
support the same address translation mechanism that requires an intermediate 52-bit virtual
address. It also does not support block address translation or the associated block address
translation SPRs. In its place, the MPC860Õs internal memory space includes memory-mapped
control registers and memory used by various modules on the chip. This memory is part of the main
memory as seen by the core but cannot be accessed by any external system device.
MOTOROLA
Table 4-4. VEA-Level Features (Continued)
Table 4-5. OEA-Level Features
Chapter 4. The PowerPC Core
Part II. PowerPC Microprocessor Module
Description
Description
4-17
Advertisement
Table of Contents
