Motorola MPC860 PowerQUICC User Manual page 601

21.2.3.5 One TDM Channel with Dynamic Frames
In an SI conÞguration using one TDM channel with dynamic frames, TDMa has 32 entries
apiece for Tx and Rx data/strobe routing, as shown in Figure 21-8. One RAM partition is
the current-route RAM; the other is shadow RAM that can be safely reprogrammed. After
programming the shadow RAM, set the CSRx bit of the channel in the SI command register
(SICMR). When the next frame sync arrives, the SI swaps the current-route RAM with the
shadow RAM.
SI RAM Address:
(32-Bit Entries)
Figure 21-8. SI RAM Partitioning Using TDMa with Dynamic Frames
21.2.3.6 Two TDM Channels with Dynamic Frames
In an SI conÞguration using both TDM channels with dynamic frames, each channel has 16
entries apiece for Tx and Rx data/strobe routing, as shown in Figure 21-9. One partition is
the current-route RAM; the other is shadow RAM that can be safely reprogrammed. After
programming the shadow RAM, the user sets SICMR[CSRx]. When the next frame sync
arrives, the SI swaps the current-route RAM with the shadow RAM.
SI RAM Address: 0
(32-Bit Entries)
16 Entries
63
256
16 Entries
319
Figure 21-9. SI RAM Partitioning Using Two TDMs with Dynamic Frames
MOTOROLA
RDM = 01
TDMa with Shadow RAM for Dynamic Route Changes
0
32 Entries
RXa
Route
127
256
32 Entries
TXa
Route
383
RDM = 11
Two Channels with Shadow RAM for Dynamic Route Changes
Framing Signals
64
L1RCLKa
RXa
L1RSYNCa
Route
Shadow
127
320
L1TCLKa
TXa
L1TSYNCa
Route
Shadow
383
Chapter 21. Serial Interface
Part V. The Communications Processor Module
Framing Signals
128
L1RCLKa
L1RSYNCa
Shadow
255
384
L1TCLKa
L1TSYNCa
Shadow
511
128
16 Entries
RXb
Route
191
384
16 Entries
TXb
Route
447
Framing Signals
192
L1RCLKb
L1RSYNCb
Shadow
255
448
L1TCLKb
L1TSYNCb
Shadow
511
21-13