Motorola MPC860 PowerQUICC User Manual page 868

Part V. The Communications Processor Module
Bit 0 1 2
Field STR Ñ
Reset
R/W
Addr
Figure 33-5. PIP Configuration Register (PIPC)
Table 33-6 describes PIPC Þelds.
Bits Name
0 STR Start transmit. Applies when T/R = 1 (Tx operation). Setting STR causes the CP to poll the TxBD table
looking for the next TxBD in which the R-bit is set. Prepare TxBDs and buffers before setting STR. The
CP clears STR after one system clock.
1Ð3 Ñ Reserved and should be cleared.
4 SACK Set acknowledge. When set, SACK asserts the receiverÕs ACK output regardless of the receiver state.
SACK should be used to implement the IEEE P1284 bidirectional Centronics protocol.
5 CBSY Clear BUSY. When CBSY is set, BUSY is driven low. CBSY is automatically cleared after the PIP
negates BUSY. Set EBSY before using SBSY or CBSY. Note that PIPC[T/R] should be cleared
(receiving) if SBSY or CBSY are used.
6 SBSY Set BUSY. When SBSY is set, BUSY is driven high. SBSY is automatically cleared after the PIP
asserts BUSY. Set EBSY before using SBSY or CBSY. Note that PIPC[T/R] should be cleared
(receiving) if SBSY or CBSY are used.
7 EBSY Enable BUSY. The bit deÞnition depends on whether T/R is set to receive or transmit. BUSY is not
affected by MODL programming if EBSY = 1.
T/R = 0 (Receiving):
0 Disable BUSY signal generation on PB31 for the receiver.
1 Enable the BUSY output on PB31. EBSY takes effect only if BUSY is conÞgured as a PIP output
(PBPAR[31] = 0 and PBDIR[31] = 1).
T/R = 1 (Transmitting):
0 Ignore the BUSY input on PB31 for the transmitter.
1 Assertion of STB requires negation of BUSY. STB is not asserted until BUSY, input on PB31, is
negated. EBSY takes effect only if BUSY is conÞgured as a PIP input (PBPAR[31] = PBDIR[31] = 0).
8Ð9 TMOD Timing mode. Used to implement a Centronics-type receiver. Valid only when T/R = 0 (Rx operation)
and MODH = 11 (pulsed handshake). For the deÞnition of these timing modes, see Section 33.7.2.2,
ÒPulsed Handshake Timing.Ó
00 PIP receiver timing mode 0.
01 PIP receiver timing mode 1.
10 PIP receiver timing mode 2.
11 PIP receiver timing mode 3.
10Ð MODL Mode low. Determines the mode of the PIPÕs lower 8 signals, PB[24Ð31], which extend the PIP
11 interface to 16 bits. (If the PIP is 8-bit, program MODL to 0b00.)
00 Port B general-purpose I/O
01 Transparent transfer modeÑcontrolled by the CP.
1x Mode of operation is controlled by MODH.
Note that BUSY is not affected by MODL programming if EBSY = 1.
33-8
3 4 5 6
SACK CBSY SBSY EBSY
0000_0000_0000_0000
Table 33-6. PIPC Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7 8 9 10
TMOD MODL
R/W
0xAB2
Description
11 12 13 14 15
MODH HSC T/R
MOTOROLA