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ICR protection is described in Table 37-15 Table 37-24 describes ICR Þelds.
Bits
Name
0
Ñ
Reserved
1
RST
Reset interrupt bit. Set when the SRESET is asserted.
2
CHSTP
Check stop bit. Set when the machine check interrupt is asserted and MSR[ME] = 0. Results in
debug mode entry if debug mode is enabled and the corresponding enable bit is set. Otherwise,
the processor enters checkstop state.
3
MCI
Machine check interrupt bit. Set when the machine check interrupt is asserted and MSR[ME]
=1. Causes debug mode entry if debug mode is enabled and the corresponding enable bit is
set.
4Ð5
Ñ
Reserved
6
EXTI
External interrupt bit. Set when the external interrupt is asserted. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
7
ALI
Alignment interrupt bit. Set when the alignment interrupt is asserted. Causes debug mode entry
if debug mode is enabled and the corresponding enable bit is set.
8
PRI
Program interrupt bit. Set when the program interrupt is asserted. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
9
FPUVI
Floating-point unavailable interrupt bit. Set when the ßoating-point unavailable interrupt is
asserted. Causes debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
10
DECI
Decrementer interrupt bit. Set when the decrementer interrupt is asserted. Causes debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
11Ð1
Ñ
Reserved
2
13
SYSI
System call interrupt bit. Set when the system call interrupt is asserted. Causes debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
14
TR
Trace interrupt bit. Set when in single-step mode or when in branch trace mode. Causes debug
mode entry if debug mode is enabled and the corresponding enable bit is set.
15Ð1
Ñ
Reserved
6
17
SEI
Implementation-dependent software emulation interrupt. Set when the ßoating-point assist
interrupt is asserted. Causes debug mode entry if debug mode is enabled and the
corresponding enable bit is set.
18
ITLBM
Implementation-speciÞc ITLB miss. Set as a result of an ITLB miss. Causes debug mode entry
S
if debug mode is enabled and the corresponding enable bit is set.
19
DTLBM
Implementation-speciÞc DTLB miss. Set as a result of an DTLB miss. Causes debug mode
S
entry if debug mode is enabled and the corresponding enable bit is set.
20
ITLBER
Implementation-speciÞc ITLB error. Set as a result of an ITLB error. Causes debug mode entry
if debug mode is enabled and the corresponding enable bit is set.
21
DTLBE
Implementation-speciÞc DTLB error. Set as a result of an DTLB error. results in debug mode
R
entry if debug mode is enabled and the corresponding enable bit is set.
MOTOROLA
Table 37-24. ICR Field Descriptions
Chapter 37. System Development and Debugging
Description
Part VI. Debug and Test
37-45
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