Motorola MPC860 PowerQUICC User Manual page 399

Part IV. Hardware Interface
designs to fail. This risk should be taken into account when the design is performed; if
potential manufacturing downtime due to redesign of crystal circuits is unacceptable, then
a canned oscillator circuit should be used instead.
Crystal
C1 R2 C2
R1
EXTAL XTAL
A5 A4
OSCM
32 KHz: R1=20MW, R2=330KW, C1=20pF, C2=20pF
4 MHz: R1=10MW, R2=1KW, C1=47 pF, C2=56 pF
Figure 15-3.Crystal Circuit Examples
15.2.2 System PLL
The programmable phase-locked loop, called the system phase-locked loop (SPLL) in the
MPC860 , generates the overall system operating frequency in integer multiples of the input
clock frequency. The SPLL reference clock (OSCCLK) can be generated from either of the
external clock sources described in Section 15.2.1, ÒExternal Reference Clocks.Ó
The main purpose of the SPLL is to generate a stable reference frequency by multiplying
the frequency and eliminating the clock skew. The SPLL allows the processor to operate at
a high internal clock frequency using a low frequency clock input, providing two
advantages. First, lower frequency clock input reduces the overall electromagnetic
interference generated by the system. Second, the programmability of the oscillator enables
the system to operate at a variety of frequencies with only a single external clock source.
The MPC860 SPLL block diagram is shown in Figure 15-4.
MOTOROLA Chapter 15. Clocks and Power Control 15-5