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request is considered pending and remains pending until it is processed. Subsequent
requests on DREQ are ignored until the pending request is acknowledged.
20.3.8 IDMA TransfersÑDual-Address and Single-Address
Once an IDMA channel successfully arbitrates for the bus, it begins the transfer. An IDMA
channel has the same bus cycle timing as the other internal masters.
The IDMA controller supports both dual- and single-address transfers. The dual-address
transfer consists of a source read and a destination writeÑa memory/memory or
memory/peripheral transfer. A single-address transfer, also called ßy-by, consists of one
external read or write bus cycleÑa memory/peripheral transfer.
20.3.8.1 Dual-Address (Dual-Cycle) Transfer
The IDMA channels can operate in a dual-address transfer mode in which data is Þrst read
using the source pointer and placed in internal storage. The data operand is then packed
onto the bus and written to the address given by the destination pointer. The read and write
transfers can take several bus cycles each because of differences in the source and
destination operand sizes. The dual-address read and write cycles are described below.
¥ Dual-address source readÑSAPR drives the address bus, SFCR drives the address
type, and DCMR drives the size control. Data is read from the memory or peripheral
and placed in internal storage at the end of the bus cycle. For memory reads, SAPR
is automatically incremented by 1, 2, 4, or 16, depending on the address and size
information speciÞed by DCMR. See Section 20.3.2, ÒIDMA Parameter RAM,Ó and
Section 20.3.3.1, ÒDMA Channel Mode Registers (DCMR).Ó
¥ Dual-address destination writeÑThe data in internal storage is written to the
peripheral or memory governed by the address in DAPR, the address type in DFCR,
and the size in DCMR. For memory writes, DAPR is automatically incremented by
1, 2, 4, or 16 according to DCMR. The byte count is decremented by the number of
bytes transferred. When the byte count reaches zero and the transfer reports no
errors, IDSR[DONE] is ßagged, which triggers a maskable interrupt. See
Section 20.3.2, ÒIDMA Parameter RAM,Ó and Section 20.3.3, ÒIDMA Registers.Ó
Additionally, for peripheral/memory dual-address transfers, the SDACK signal asserts
during the peripheral access. For dual-address transfers, microcode performs byte-packing
using a 16-byte buffer in the dual-port RAM. Regardless of the source size, destination size,
source starting address, or destination starting address, IDMA uses the most efÞcient
packing algorithm possible to perform the transfer in the least number of bus cycles.
20.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By)
Each IDMA channel can be independently programmed to provide single-address, or
ßy-by, transfers. The IDMA channel bypasses or Òßys-byÓ internal storage since the
transfer occurs directly between a device and memory. DCMR[S/D] controls the direction
of the transfer. If DCMR[S/D] = 0b01, the IDMA controller handshakes with the peripheral
for the source data and writes to the destination memory address provided. If
MOTOROLA
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
20-15
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