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Figure 18-3 is a block diagram of the CPM timers.
TGCR
Global Configuration Register
TER1
Mode Register
TMR1
Prescaler
Divider
TCN1
Timer Counter (TCN)
TRR1
Reference Register (TRR)
TCR1
Capture Register (TCR)
Timer1
Timer2
Timer3
Timer4
18.2.1 Features
The following list summarizes the main features of the CPM timers:
¥ Maximum period of 10.7 seconds (at 25 MHz)
¥ 40-ns resolution (at 25 MHz)
¥ Programmable sources for the clock input
¥ Input capture capability
¥ Output compare with programmable mode for the output pin
¥ Timers are cascadeable to form 32-bit timers
¥ Free run and restart modes
¥ Functionally compatible with MC68360 timers
18.2.2 CPM Timer Operation
The following subsections describe the timer operation. The timer mode registers (TMRx)
and the timer global conÞguration register (TGCR) mentioned in this section are described
in Section 18.2.3, ÒCPM Timer Register Set.Ó
MOTOROLA
Chapter 18. Communications Processor Module and CPM Timers
Event Register
Mode Bits
Clock
Figure 18-3. CPM Timer Block Diagram
Part V. The Communications Processor Module
General
System Clock
Timer
Clock
Generator
Capture
Detection
TGATE1
TGATE2
TIN1
TIN2
TIN3
TIN4
TOUT1
TOUT2
TOUT3
TOUT4
18-5
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